Mesa (master): aco: do not use the vec3 variant for stores on GFX6

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Module: Mesa
Branch: master
Commit: 1b5bb204d9724e166b33dc03bb187499088f278d
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b5bb204d9724e166b33dc03bb187499088f278d

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Jan 16 14:37:11 2020 +0100

aco: do not use the vec3 variant for stores on GFX6

GFX6 only supports vec3 with load/store format.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-By: Timur Kristóf <timur.kristof at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3432>

---

 src/amd/compiler/aco_instruction_selection.cpp | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 6d6d806a2d0..250f7011b04 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -4501,7 +4501,8 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
    while (writemask) {
       int start, count;
       u_bit_scan_consecutive_range(&writemask, &start, &count);
-      if (count == 3 && smem) {
+      if (count == 3 && (smem || ctx->options->chip_class == GFX6)) {
+         /* GFX6 doesn't support storing vec3, split it. */
          writemask |= 1u << (start + 2);
          count = 2;
       }
@@ -4551,7 +4552,7 @@ void visit_store_ssbo(isel_context *ctx, nir_intrinsic_instr *instr)
          case 12:
             vmem_op = aco_opcode::buffer_store_dwordx3;
             smem_op = aco_opcode::last_opcode;
-            assert(!smem);
+            assert(!smem && ctx->options->chip_class > GFX6);
             break;
          case 16:
             vmem_op = aco_opcode::buffer_store_dwordx4;