Mesa (master): intel/compiler: Add NF some more places

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Module: Mesa
Branch: master
Commit: ab7c25b9aa241b2754a48fc04fd4752a511b7a2c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab7c25b9aa241b2754a48fc04fd4752a511b7a2c

Author: Matt Turner <mattst88 at gmail.com>
Date:   Thu Jan  2 14:54:34 2020 -0800

intel/compiler: Add NF some more places

Necessary to handle these cases when we test fuzzed instructions.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2635>

---

 src/intel/compiler/brw_eu_validate.c | 4 ++++
 src/intel/compiler/brw_reg.h         | 1 +
 2 files changed, 5 insertions(+)

diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c
index 5953c82bc70..efd7787c00d 100644
--- a/src/intel/compiler/brw_eu_validate.c
+++ b/src/intel/compiler/brw_eu_validate.c
@@ -475,6 +475,10 @@ execution_type(const struct gen_device_info *devinfo, const brw_inst *inst)
    if (src0_exec_type == src1_exec_type)
       return src0_exec_type;
 
+   if (src0_exec_type == BRW_REGISTER_TYPE_NF ||
+       src1_exec_type == BRW_REGISTER_TYPE_NF)
+      return BRW_REGISTER_TYPE_NF;
+
    /* Mixed operand types where one is float is float on Gen < 6
     * (and not allowed on later platforms)
     */
diff --git a/src/intel/compiler/brw_reg.h b/src/intel/compiler/brw_reg.h
index 4543d841c66..a85b10e09f9 100644
--- a/src/intel/compiler/brw_reg.h
+++ b/src/intel/compiler/brw_reg.h
@@ -318,6 +318,7 @@ type_sz(unsigned type)
    case BRW_REGISTER_TYPE_UQ:
    case BRW_REGISTER_TYPE_Q:
    case BRW_REGISTER_TYPE_DF:
+   case BRW_REGISTER_TYPE_NF:
       return 8;
    case BRW_REGISTER_TYPE_UD:
    case BRW_REGISTER_TYPE_D: