Mesa (master): aco: value-number MUBUF instructions
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Tue Jan 28 12:07:56 UTC 2020
Module: Mesa
Branch: master
Commit: 21d2799cee8d5fa01b118a8afe595759b4f22cab
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21d2799cee8d5fa01b118a8afe595759b4f22cab
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Fri Jan 3 17:38:23 2020 +0000
aco: value-number MUBUF instructions
We will have to do this when we start creating MUBUF instructions for
load_input because NIR might not be able to tell they are identical since
it doesn't know whether two vertex attributes have the same offset.
No pipeline-db changes.
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3086>
---
src/amd/compiler/aco_opt_value_numbering.cpp | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/src/amd/compiler/aco_opt_value_numbering.cpp b/src/amd/compiler/aco_opt_value_numbering.cpp
index 295a4343854..2f5a3b8eec9 100644
--- a/src/amd/compiler/aco_opt_value_numbering.cpp
+++ b/src/amd/compiler/aco_opt_value_numbering.cpp
@@ -184,7 +184,6 @@ struct InstrPred {
aR->cluster_size == bR->cluster_size;
}
case Format::MTBUF: {
- /* this is fine since they are only used for vertex input fetches */
MTBUF_instruction* aM = static_cast<MTBUF_instruction *>(a);
MTBUF_instruction* bM = static_cast<MTBUF_instruction *>(b);
return aM->can_reorder && bM->can_reorder &&
@@ -195,12 +194,27 @@ struct InstrPred {
aM->offen == bM->offen &&
aM->idxen == bM->idxen &&
aM->glc == bM->glc &&
+ aM->dlc == bM->dlc &&
aM->slc == bM->slc &&
aM->tfe == bM->tfe &&
aM->disable_wqm == bM->disable_wqm;
}
+ case Format::MUBUF: {
+ MUBUF_instruction* aM = static_cast<MUBUF_instruction *>(a);
+ MUBUF_instruction* bM = static_cast<MUBUF_instruction *>(b);
+ return aM->can_reorder && bM->can_reorder &&
+ aM->barrier == bM->barrier &&
+ aM->offset == bM->offset &&
+ aM->offen == bM->offen &&
+ aM->idxen == bM->idxen &&
+ aM->glc == bM->glc &&
+ aM->dlc == bM->dlc &&
+ aM->slc == bM->slc &&
+ aM->tfe == bM->tfe &&
+ aM->lds == bM->lds &&
+ aM->disable_wqm == bM->disable_wqm;
+ }
/* we want to optimize these in NIR and don't hassle with load-store dependencies */
- case Format::MUBUF:
case Format::FLAT:
case Format::GLOBAL:
case Format::SCRATCH:
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