Mesa (master): tu: Fix binning address setup after pack macros change.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 06b13dfed2a43d5f14d6886dfced9b5befcc159b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=06b13dfed2a43d5f14d6886dfced9b5befcc159b

Author: Eric Anholt <eric at anholt.net>
Date:   Tue Jan 28 16:00:45 2020 -0800

tu: Fix binning address setup after pack macros change.

This fixes a regression in "vkcube -m headless" rendering, but upsettingly
none of my CTS tests I've been using.

Fixes: 59f29fc845ce ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")
Caught-by: Jonathan Marek <jonathan at marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>

---

 src/freedreno/vulkan/tu_cmd_buffer.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c
index 4cb47cef946..a11cab52945 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -1092,7 +1092,8 @@ update_vsc_pipe(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
    tu_cs_emit_regs(cs,
                    A6XX_VSC_BIN_SIZE(.width = tiling->tile0.extent.width,
                                      .height = tiling->tile0.extent.height),
-                   A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data, .bo_offset = cmd->vsc_data_pitch));
+                   A6XX_VSC_SIZE_ADDRESS(.bo = &cmd->vsc_data,
+                                         .bo_offset = 32 * cmd->vsc_data_pitch));
 
    tu_cs_emit_regs(cs,
                    A6XX_VSC_BIN_COUNT(.nx = tiling->tile_count.width,