Mesa (master): freedreno: get GMEM state from batch
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Wed Jan 29 21:42:47 UTC 2020
Module: Mesa
Branch: master
Commit: 712f8802ee248713821e8d649263257e67c5d597
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=712f8802ee248713821e8d649263257e67c5d597
Author: Rob Clark <robdclark at chromium.org>
Date: Tue Jan 21 11:27:14 2020 -0800
freedreno: get GMEM state from batch
Prep work to reduce churn in next patch.
Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
---
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 8 +++----
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 25 +++++++++++-----------
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c | 22 +++++++++----------
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c | 23 +++++++++-----------
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 28 ++++++++++++-------------
src/gallium/drivers/freedreno/freedreno_batch.h | 6 ++++++
src/gallium/drivers/freedreno/freedreno_gmem.c | 6 +++---
7 files changed, 59 insertions(+), 59 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 63e5078c0c8..0ba2b4acb45 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -62,7 +62,7 @@ static uint32_t fmt2swap(enum pipe_format format)
static bool
use_hw_binning(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
/* we hardcoded a limit of 8 "pipes", we can increase this limit
* at the cost of a slightly larger command stream
@@ -136,7 +136,7 @@ prepare_tile_fini_ib(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd2_context *fd2_ctx = fd2_context(ctx);
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring;
@@ -277,7 +277,7 @@ fd2_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
struct fd2_context *fd2_ctx = fd2_context(ctx);
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
unsigned bin_w = tile->bin_w;
@@ -478,7 +478,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
enum pipe_format format = pipe_surface_format(pfb->cbufs[0]);
uint32_t reg;
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index b7c02915d4a..90c8b8bd49f 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -129,7 +129,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
static bool
use_hw_binning(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
/* workaround: combining scissor optimization and hw binning
* seems problematic. Seems like we end up with a mismatch
@@ -163,7 +163,7 @@ static void
emit_binning_workaround(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
struct fd3_emit emit = {
.debug = &ctx->debug,
@@ -361,6 +361,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd3_emit emit = {
.debug = &ctx->debug,
@@ -419,7 +420,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
OUT_RING(ring, A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE |
A3XX_RB_RENDER_CONTROL_ENABLE_GMEM |
A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(FUNC_NEVER) |
- A3XX_RB_RENDER_CONTROL_BIN_WIDTH(ctx->gmem.bin_w));
+ A3XX_RB_RENDER_CONTROL_BIN_WIDTH(batch->gmem_state->bin_w));
OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
OUT_RING(ring, A3XX_GRAS_SC_CONTROL_RENDER_MODE(RB_RESOLVE_PASS) |
@@ -451,10 +452,10 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
if (!rsc->stencil || batch->resolve & FD_BUFFER_DEPTH)
emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, false,
- ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+ gmem->zsbuf_base[0], pfb->zsbuf);
if (rsc->stencil && batch->resolve & FD_BUFFER_STENCIL)
emit_gmem2mem_surf(batch, RB_COPY_DEPTH_STENCIL, true,
- ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+ gmem->zsbuf_base[1], pfb->zsbuf);
}
if (batch->resolve & FD_BUFFER_COLOR) {
@@ -464,7 +465,7 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
if (!(batch->resolve & (PIPE_CLEAR_COLOR0 << i)))
continue;
emit_gmem2mem_surf(batch, RB_COPY_RESOLVE, false,
- ctx->gmem.cbuf_base[i], pfb->cbufs[i]);
+ gmem->cbuf_base[i], pfb->cbufs[i]);
}
}
@@ -512,7 +513,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, const uint32_t bases[],
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_INFO, 2);
OUT_RING(ring, A3XX_RB_DEPTH_INFO_DEPTH_BASE(bases[0]) |
A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(DEPTHX_32));
- OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->ctx->gmem.bin_w));
+ OUT_RING(ring, A3XX_RB_DEPTH_PITCH(4 * batch->gmem_state->bin_w));
if (psurf[0]->format == PIPE_FORMAT_Z32_FLOAT) {
OUT_PKT0(ring, REG_A3XX_RB_MRT_CONTROL(0), 1);
@@ -541,7 +542,7 @@ static void
fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd3_emit emit = {
@@ -777,7 +778,7 @@ static void
update_vsc_pipe(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -807,7 +808,7 @@ static void
emit_binning_pass(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -936,7 +937,7 @@ fd3_emit_tile_init(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
uint32_t rb_render_control;
fd3_emit_restore(batch, ring);
@@ -990,7 +991,7 @@ fd3_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
struct fd_context *ctx = batch->ctx;
struct fd3_context *fd3_ctx = fd3_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
uint32_t x1 = tile->xoff;
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 6814722da75..16e2ac0fbad 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -132,7 +132,7 @@ emit_mrt(struct fd_ringbuffer *ring, unsigned nr_bufs,
static bool
use_hw_binning(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
if ((gmem->maxpw * gmem->maxph) > 32)
return false;
@@ -190,7 +190,7 @@ static void
fd4_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
@@ -274,9 +274,9 @@ fd4_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
if (!rsc->stencil || (batch->resolve & FD_BUFFER_DEPTH))
- emit_gmem2mem_surf(batch, false, ctx->gmem.zsbuf_base[0], pfb->zsbuf);
+ emit_gmem2mem_surf(batch, false, gmem->zsbuf_base[0], pfb->zsbuf);
if (rsc->stencil && (batch->resolve & FD_BUFFER_STENCIL))
- emit_gmem2mem_surf(batch, true, ctx->gmem.zsbuf_base[1], pfb->zsbuf);
+ emit_gmem2mem_surf(batch, true, gmem->zsbuf_base[1], pfb->zsbuf);
}
if (batch->resolve & FD_BUFFER_COLOR) {
@@ -328,7 +328,7 @@ static void
fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd4_emit emit = {
@@ -561,7 +561,7 @@ static void
update_vsc_pipe(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -596,8 +596,7 @@ update_vsc_pipe(struct fd_batch *batch)
static void
emit_binning_pass(struct fd_batch *batch)
{
- struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -664,7 +663,7 @@ fd4_emit_tile_init(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
fd4_emit_restore(batch, ring);
@@ -707,10 +706,9 @@ fd4_emit_tile_init(struct fd_batch *batch)
static void
fd4_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
{
- struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
if (pfb->zsbuf) {
struct fd_resource *rsc = fd_resource(pfb->zsbuf->texture);
@@ -758,7 +756,7 @@ fd4_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
struct fd_context *ctx = batch->ctx;
struct fd4_context *fd4_ctx = fd4_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
uint32_t x1 = tile->xoff;
diff --git a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
index f944877a514..d2d53832748 100644
--- a/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+++ b/src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
@@ -234,7 +234,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
static bool
use_hw_binning(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
if ((gmem->maxpw * gmem->maxph) > 32)
return false;
@@ -262,7 +262,7 @@ update_vsc_pipe(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd5_context *fd5_ctx = fd5_context(ctx);
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -304,7 +304,7 @@ emit_binning_pass(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
uint32_t x1 = gmem->minx;
uint32_t y1 = gmem->miny;
@@ -366,7 +366,6 @@ emit_binning_pass(struct fd_batch *batch)
static void
fd5_emit_tile_init(struct fd_batch *batch)
{
- struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
@@ -394,8 +393,8 @@ fd5_emit_tile_init(struct fd_batch *batch)
OUT_PKT4(ring, REG_A5XX_RB_CCU_CNTL, 1);
OUT_RING(ring, 0x7c13c080); /* RB_CCU_CNTL */
- emit_zs(ring, pfb->zsbuf, &ctx->gmem);
- emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, &ctx->gmem);
+ emit_zs(ring, pfb->zsbuf, batch->gmem_state);
+ emit_mrt(ring, pfb->nr_cbufs, pfb->cbufs, batch->gmem_state);
if (use_hw_binning(batch)) {
emit_binning_pass(batch);
@@ -413,7 +412,7 @@ static void
fd5_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd5_context *fd5_ctx = fd5_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
@@ -469,7 +468,7 @@ emit_mem2gmem_surf(struct fd_batch *batch, uint32_t base,
struct pipe_surface *psurf, enum a5xx_blit_buf buf)
{
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_resource *rsc = fd_resource(psurf->texture);
uint32_t stride, size;
@@ -525,8 +524,7 @@ static void
fd5_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_ringbuffer *ring = batch->gmem;
- struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
/*
@@ -569,7 +567,7 @@ static void
fd5_emit_tile_renderprep(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
OUT_PKT4(ring, REG_A5XX_RB_CNTL, 1);
@@ -654,8 +652,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, uint32_t base,
static void
fd5_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
{
- struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (batch->resolve & (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL)) {
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index df022eacaa3..28388bfb8a2 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -265,7 +265,7 @@ emit_zs(struct fd_ringbuffer *ring, struct pipe_surface *zsbuf,
static bool
use_hw_binning(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
// TODO figure out hw limits for binning
@@ -276,7 +276,7 @@ use_hw_binning(struct fd_batch *batch)
static void
patch_fb_read(struct fd_batch *batch)
{
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
for (unsigned i = 0; i < fd_patch_num_elements(&batch->fb_read_patches); i++) {
struct fd_cs_patch *patch = fd_patch_element(&batch->fb_read_patches, i);
@@ -332,7 +332,7 @@ update_vsc_pipe(struct fd_batch *batch)
{
struct fd_context *ctx = batch->ctx;
struct fd6_context *fd6_ctx = fd6_context(ctx);
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd_ringbuffer *ring = batch->gmem;
int i;
@@ -400,7 +400,7 @@ static void
emit_vsc_overflow_test(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
debug_assert((fd6_ctx->vsc_data_pitch & 0x3) == 0);
@@ -608,7 +608,7 @@ static void
emit_binning_pass(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
uint32_t x1 = gmem->minx;
@@ -723,7 +723,7 @@ fd6_emit_tile_init(struct fd_batch *batch)
struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
fd6_emit_restore(batch, ring);
@@ -744,8 +744,8 @@ fd6_emit_tile_init(struct fd_batch *batch)
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
- emit_zs(ring, pfb->zsbuf, &ctx->gmem);
- emit_mrt(ring, pfb, &ctx->gmem);
+ emit_zs(ring, pfb->zsbuf, batch->gmem_state);
+ emit_mrt(ring, pfb, batch->gmem_state);
emit_msaa(ring, pfb->samples);
patch_fb_read(batch);
@@ -822,7 +822,7 @@ static void
fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
{
struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd_ringbuffer *ring = batch->gmem;
@@ -884,7 +884,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
set_window_offset(ring, x1, y1);
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
set_bin_size(ring, gmem->bin_w, gmem->bin_h, 0x6000000);
OUT_PKT7(ring, CP_SET_MODE, 1);
@@ -1004,7 +1004,7 @@ static void
emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
- const struct fd_gmem_stateobj *gmem = &batch->ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
enum a3xx_msaa_samples samples = fd_msaa_samples(pfb->samples);
uint32_t buffers = batch->fast_cleared;
@@ -1167,8 +1167,7 @@ emit_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
static void
emit_restore_blits(struct fd_batch *batch, struct fd_ringbuffer *ring)
{
- struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
if (batch->restore & FD_BUFFER_COLOR) {
@@ -1269,8 +1268,7 @@ emit_resolve_blit(struct fd_batch *batch,
static void
prepare_tile_fini_ib(struct fd_batch *batch)
{
- struct fd_context *ctx = batch->ctx;
- const struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ const struct fd_gmem_stateobj *gmem = batch->gmem_state;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
struct fd_ringbuffer *ring;
diff --git a/src/gallium/drivers/freedreno/freedreno_batch.h b/src/gallium/drivers/freedreno/freedreno_batch.h
index 5061186f1b5..9d6defc7564 100644
--- a/src/gallium/drivers/freedreno/freedreno_batch.h
+++ b/src/gallium/drivers/freedreno/freedreno_batch.h
@@ -125,6 +125,12 @@ struct fd_batch {
FD_GMEM_LOGICOP_ENABLED = 0x20,
FD_GMEM_FB_READ = 0x40,
} gmem_reason;
+
+ /* At submit time, once we've decided that this batch will use GMEM
+ * rendering, the appropriate gmem state is looked up:
+ */
+ const struct fd_gmem_stateobj *gmem_state;
+
unsigned num_draws; /* number of draws in current batch */
unsigned num_vertices; /* number of vertices in current batch */
diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c
index 0a960859a6c..840ba86d6eb 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.c
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.c
@@ -347,10 +347,9 @@ calculate_tiles(struct fd_batch *batch)
}
static void
-render_tiles(struct fd_batch *batch)
+render_tiles(struct fd_batch *batch, struct fd_gmem_stateobj *gmem)
{
struct fd_context *ctx = batch->ctx;
- struct fd_gmem_stateobj *gmem = &ctx->gmem;
int i;
ctx->emit_tile_init(batch);
@@ -485,6 +484,7 @@ fd_gmem_render_tiles(struct fd_batch *batch)
ctx->stats.batch_sysmem++;
} else {
struct fd_gmem_stateobj *gmem = &ctx->gmem;
+ batch->gmem_state = gmem;
calculate_tiles(batch);
DBG("%p: rendering %dx%d tiles %ux%u (%s/%s)",
batch, pfb->width, pfb->height, gmem->nbins_x, gmem->nbins_y,
@@ -492,7 +492,7 @@ fd_gmem_render_tiles(struct fd_batch *batch)
util_format_short_name(pipe_surface_format(pfb->zsbuf)));
if (ctx->query_prepare)
ctx->query_prepare(batch, gmem->nbins_x * gmem->nbins_y);
- render_tiles(batch);
+ render_tiles(batch, gmem);
ctx->stats.batch_gmem++;
}
More information about the mesa-commit
mailing list