Mesa (staging/19.3): aco: fix target calculation when vgpr spilling introduces sgpr spilling

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Module: Mesa
Branch: staging/19.3
Commit: 15bfd1393bd37ef8c408855afc0afcbb680c22b9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=15bfd1393bd37ef8c408855afc0afcbb680c22b9

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Thu Jan  2 15:36:49 2020 +0000

aco: fix target calculation when vgpr spilling introduces sgpr spilling

A shader might require vgpr spilling but not require sgpr spilling. In
that case, the spiller lowers the sgpr target by 5 which could mean sgpr
spilling is then required. Then the vgpr target has to be lowered to make
space for the linear vgprs. Previously, space wasn't make for the linear
vgprs.

Found while testing the spiller on the pipeline-db with a lowered limit

Fixes: a7ff1bb5b9a78cf57073b5e2e136daf0c85078d6
   ('aco: simplify calculation of target register pressure when spilling')

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
(cherry picked from commit 590c26beab153fbc7c2193ce65a9a63329a80be8)

Conflicts:
	src/amd/compiler/aco_spill.cpp

---

 .pick_status.json              | 2 +-
 src/amd/compiler/aco_spill.cpp | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index e27ac62433e..082452dfa95 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -418,7 +418,7 @@
         "description": "aco: fix target calculation when vgpr spilling introduces sgpr spilling",
         "nominated": true,
         "nomination_type": 1,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": "a7ff1bb5b9a78cf57073b5e2e136daf0c85078d6"
     },
diff --git a/src/amd/compiler/aco_spill.cpp b/src/amd/compiler/aco_spill.cpp
index cc662e97418..fb55064adf5 100644
--- a/src/amd/compiler/aco_spill.cpp
+++ b/src/amd/compiler/aco_spill.cpp
@@ -1744,9 +1744,8 @@ void spill(Program* program, live& live_vars, const struct radv_nir_compiler_opt
 
    if (register_target.vgpr > program->vgpr_limit)
       register_target.sgpr = program->sgpr_limit - 5;
-   register_target.vgpr = program->vgpr_limit - (register_target.vgpr - program->max_reg_demand.vgpr);
-
-   int spills_to_vgpr = (program->max_reg_demand.sgpr - register_target.sgpr + 63 + 32) / 64;
+   int spills_to_vgpr = (program->max_reg_demand.sgpr - register_target.sgpr + program->wave_size - 1 + 32) / program->wave_size;
+   register_target.vgpr = program->vgpr_limit - spills_to_vgpr;
 
    /* initialize ctx */
    spill_ctx ctx(register_target, program, live_vars.register_demand);