Mesa (master): intel/common: Return the block size from get_urb_config
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Fri Jan 31 05:36:38 UTC 2020
Module: Mesa
Branch: master
Commit: fdc0c19328fd8e02e4b1bd5c62b93ce6c4597ca1
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdc0c19328fd8e02e4b1bd5c62b93ce6c4597ca1
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Fri Jan 17 14:10:40 2020 -0600
intel/common: Return the block size from get_urb_config
Cc: "20.0" mesa-stable at lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
---
src/gallium/drivers/iris/iris_state.c | 2 +-
src/intel/blorp/blorp_genX_exec.h | 2 +-
src/intel/common/gen_l3_config.h | 9 +++++++-
src/intel/common/gen_urb_config.c | 42 ++++++++++++++++++++++++++++++++++-
src/intel/vulkan/genX_pipeline.c | 2 +-
src/mesa/drivers/dri/i965/gen7_urb.c | 3 ++-
6 files changed, 54 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index f5bcc681ab1..721edca7026 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -5386,7 +5386,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
batch->screen->l3_config_3d,
ice->shaders.prog[MESA_SHADER_TESS_EVAL] != NULL,
ice->shaders.prog[MESA_SHADER_GEOMETRY] != NULL,
- size, entries, start);
+ size, entries, start, NULL);
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
iris_emit_cmd(batch, GENX(3DSTATE_URB_VS), urb) {
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index d271bb4248c..3cd2ce6d048 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -218,7 +218,7 @@ emit_urb_config(struct blorp_batch *batch,
unsigned entries[4], start[4];
gen_get_urb_config(batch->blorp->compiler->devinfo,
blorp_get_l3_config(batch),
- false, false, entry_size, entries, start);
+ false, false, entry_size, entries, start, NULL);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
diff --git a/src/intel/common/gen_l3_config.h b/src/intel/common/gen_l3_config.h
index 36414321c49..443a8949bfe 100644
--- a/src/intel/common/gen_l3_config.h
+++ b/src/intel/common/gen_l3_config.h
@@ -92,10 +92,17 @@ gen_get_l3_config_urb_size(const struct gen_device_info *devinfo,
void gen_dump_l3_config(const struct gen_l3_config *cfg, FILE *fp);
+enum gen_urb_deref_block_size {
+ GEN_URB_DEREF_BLOCK_SIZE_32 = 0,
+ GEN_URB_DEREF_BLOCK_SIZE_PER_POLY = 1,
+ GEN_URB_DEREF_BLOCK_SIZE_8 = 2,
+};
+
void gen_get_urb_config(const struct gen_device_info *devinfo,
const struct gen_l3_config *l3_cfg,
bool tess_present, bool gs_present,
const unsigned entry_size[4],
- unsigned entries[4], unsigned start[4]);
+ unsigned entries[4], unsigned start[4],
+ enum gen_urb_deref_block_size *deref_block_size);
#endif /* GEN_L3_CONFIG_H */
diff --git a/src/intel/common/gen_urb_config.c b/src/intel/common/gen_urb_config.c
index ba96966dff1..5a60ca1ef11 100644
--- a/src/intel/common/gen_urb_config.c
+++ b/src/intel/common/gen_urb_config.c
@@ -62,7 +62,8 @@ gen_get_urb_config(const struct gen_device_info *devinfo,
const struct gen_l3_config *l3_cfg,
bool tess_present, bool gs_present,
const unsigned entry_size[4],
- unsigned entries[4], unsigned start[4])
+ unsigned entries[4], unsigned start[4],
+ enum gen_urb_deref_block_size *deref_block_size)
{
const unsigned urb_size_kB = gen_get_l3_config_urb_size(devinfo, l3_cfg);
const unsigned push_constant_kB =
@@ -209,4 +210,43 @@ gen_get_urb_config(const struct gen_device_info *devinfo,
start[i] = 0;
}
}
+
+ if (deref_block_size) {
+ if (devinfo->gen >= 12) {
+ /* From the Gen12 BSpec:
+ *
+ * "Deref Block size depends on the last enabled shader and number
+ * of handles programmed for that shader
+ *
+ * 1) For GS last shader enabled cases, the deref block is
+ * always set to a per poly(within hardware)
+ *
+ * If the last enabled shader is VS or DS.
+ *
+ * 1) If DS is last enabled shader then if the number of DS
+ * handles is less than 324, need to set per poly deref.
+ *
+ * 2) If VS is last enabled shader then if the number of VS
+ * handles is less than 192, need to set per poly deref"
+ *
+ * The default is 32 so we assume that's the right choice if we're
+ * not in one of the explicit cases listed above.
+ */
+ if (gs_present) {
+ *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+ } else if (tess_present) {
+ if (entries[MESA_SHADER_TESS_EVAL] < 324)
+ *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+ else
+ *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_32;
+ } else {
+ if (entries[MESA_SHADER_VERTEX] < 192)
+ *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_PER_POLY;
+ else
+ *deref_block_size = GEN_URB_DEREF_BLOCK_SIZE_32;
+ }
+ } else {
+ *deref_block_size = 0;
+ }
+ }
}
diff --git a/src/intel/vulkan/genX_pipeline.c b/src/intel/vulkan/genX_pipeline.c
index b23be6b1152..2dd4592381d 100644
--- a/src/intel/vulkan/genX_pipeline.c
+++ b/src/intel/vulkan/genX_pipeline.c
@@ -269,7 +269,7 @@ genX(emit_urb_setup)(struct anv_device *device, struct anv_batch *batch,
active_stages &
VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT,
active_stages & VK_SHADER_STAGE_GEOMETRY_BIT,
- entry_size, entries, start);
+ entry_size, entries, start, NULL);
#if GEN_GEN == 7 && !GEN_IS_HASWELL
/* From the IVB PRM Vol. 2, Part 1, Section 3.2.1:
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c
index e04c29c833b..abc922a86a3 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -248,7 +248,8 @@ gen7_upload_urb(struct brw_context *brw, unsigned vs_size,
unsigned entries[4];
unsigned start[4];
gen_get_urb_config(devinfo, brw->l3.config,
- tess_present, gs_present, entry_size, entries, start);
+ tess_present, gs_present, entry_size,
+ entries, start, NULL);
if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail)
gen7_emit_vs_workaround_flush(brw);
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