Mesa (staging/20.0): iris: Set SLMEnable based on the L3$ config

[GitLab Mirror]

Module: Mesa
Branch: staging/20.0
Commit: 8585ae7c03b1f523ac7acb582eaa4d0dd1687e28
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8585ae7c03b1f523ac7acb582eaa4d0dd1687e28

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Fri Jan 17 11:36:52 2020 -0600

iris: Set SLMEnable based on the L3$ config

Cc: "20.0" mesa-stable at lists.freedesktop.org
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Reviewed-by: Kenneth Graunke <kenneth at whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3454>
(cherry picked from commit 6471bac99ec11c7901d6fc9bda908c047e621f5f)

---

 .pick_status.json                     | 2 +-
 src/gallium/drivers/iris/iris_state.c | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 5057fab35f8..27d60822e05 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -220,7 +220,7 @@
         "description": "iris: Set SLMEnable based on the L3$ config",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c
index e3d7256dce9..cde76bb9fb8 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -733,8 +733,8 @@ init_state_base_address(struct iris_batch *batch)
 }
 
 static void
-iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
-                    bool has_slm, bool wants_dc_cache)
+iris_emit_l3_config(struct iris_batch *batch,
+                    const struct gen_l3_config *cfg)
 {
    uint32_t reg_val;
 
@@ -748,7 +748,7 @@ iris_emit_l3_config(struct iris_batch *batch, const struct gen_l3_config *cfg,
 
    iris_pack_state(L3_ALLOCATION_REG, &reg_val, reg) {
 #if GEN_GEN < 11
-      reg.SLMEnable = has_slm;
+      reg.SLMEnable = cfg->n[GEN_L3P_SLM] > 0;
 #endif
 #if GEN_GEN == 11
       /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set
@@ -775,7 +775,7 @@ iris_emit_default_l3_config(struct iris_batch *batch, bool compute)
    const struct gen_l3_weights w =
       gen_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
    const struct gen_l3_config *cfg = gen_get_l3_config(devinfo, w);
-   iris_emit_l3_config(batch, cfg, has_slm, wants_dc_cache);
+   iris_emit_l3_config(batch, cfg);
 }
 
 #if GEN_GEN == 9