Mesa (master): pan/mdg: Remove bundle interference code

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Module: Mesa
Branch: master
Commit: 14415d581a925f9a9b1fd0273ad066b1499b5e2b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=14415d581a925f9a9b1fd0273ad066b1499b5e2b

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Jun 29 18:56:36 2020 -0400

pan/mdg: Remove bundle interference code

This incorrectly worked around the r1 issue fixed earlier.

total instructions in shared programs: 50514 -> 50509 (<.01%)
instructions in affected programs: 826 -> 821 (-0.61%)
helped: 10
HURT: 5
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.10% max: 4.17% x̄: 2.04% x̃: 1.59%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 1.16% max: 5.00% x̄: 3.10% x̃: 2.17%
95% mean confidence interval for instructions value: -0.87 0.21
95% mean confidence interval for instructions %-change: -1.90% 1.25%
Inconclusive result (value mean confidence interval includes 0).

total bundles in shared programs: 25680 -> 25675 (-0.02%)
bundles in affected programs: 539 -> 534 (-0.93%)
helped: 10
HURT: 5
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 1.54% max: 9.09% x̄: 3.51% x̃: 2.22%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 2.22% max: 8.33% x̄: 5.44% x̃: 4.17%
95% mean confidence interval for bundles value: -0.87 0.21
95% mean confidence interval for bundles %-change: -3.40% 2.35%
Inconclusive result (value mean confidence interval includes 0).

total quadwords in shared programs: 40887 -> 40887 (0.00%)
quadwords in affected programs: 0 -> 0
helped: 0
HURT: 0

total registers in shared programs: 3916 -> 3916 (0.00%)
registers in affected programs: 22 -> 22 (0.00%)
helped: 2
HURT: 2
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 16.67% max: 25.00% x̄: 20.83% x̃: 20.83%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 16.67% max: 16.67% x̄: 16.67% x̃: 16.67%
95% mean confidence interval for registers value: -1.84 1.84
95% mean confidence interval for registers %-change: -36.96% 32.79%
Inconclusive result (value mean confidence interval includes 0).

total threads in shared programs: 2455 -> 2455 (0.00%)
threads in affected programs: 0 -> 0
helped: 0
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5513>

---

 src/panfrost/midgard/midgard_ra.c | 66 ---------------------------------------
 1 file changed, 66 deletions(-)

diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 2cae4814d9f..1bc7bbf4fe1 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -309,69 +309,6 @@ mir_lower_special_reads(compiler_context *ctx)
         free(texw);
 }
 
-/* We register allocate after scheduling, so we need to ensure instructions
- * executing in parallel within a segment of a bundle don't clobber each
- * other's registers. This is mostly a non-issue thanks to scheduling, but
- * there are edge cases. In particular, after a register is written in a
- * segment, it interferes with anything reading. */
-
-static void
-mir_compute_segment_interference(
-                compiler_context *ctx,
-                struct lcra_state *l,
-                midgard_bundle *bun,
-                unsigned pivot,
-                unsigned i)
-{
-        for (unsigned j = pivot; j < i; ++j) {
-                mir_foreach_src(bun->instructions[j], s) {
-                        if (bun->instructions[j]->src[s] >= ctx->temp_count)
-                                continue;
-
-                        for (unsigned q = pivot; q < i; ++q) {
-                                if (bun->instructions[q]->dest >= ctx->temp_count)
-                                        continue;
-
-                                /* See dEQP-GLES2.functional.shaders.return.output_write_in_func_dynamic_fragment */
-
-                                if (q >= j) {
-                                        if (!(bun->instructions[j]->unit == UNIT_SMUL && bun->instructions[q]->unit == UNIT_VLUT))
-                                                continue;
-                                }
-
-                                unsigned mask = mir_bytemask(bun->instructions[q]);
-                                unsigned rmask = mir_bytemask_of_read_components(bun->instructions[j], bun->instructions[j]->src[s]);
-                                lcra_add_node_interference(l, bun->instructions[q]->dest, mask, bun->instructions[j]->src[s], rmask);
-                        }
-                }
-        }
-}
-
-static void
-mir_compute_bundle_interference(
-                compiler_context *ctx,
-                struct lcra_state *l,
-                midgard_bundle *bun)
-{
-        if (!IS_ALU(bun->tag))
-                return;
-
-        bool old = bun->instructions[0]->unit >= UNIT_VADD;
-        unsigned pivot = 0;
-
-        for (unsigned i = 1; i < bun->instruction_count; ++i) {
-                bool new = bun->instructions[i]->unit >= UNIT_VADD;
-
-                if (old != new) {
-                        mir_compute_segment_interference(ctx, l, bun, 0, i);
-                        pivot = i;
-                        break;
-                }
-        }
-
-        mir_compute_segment_interference(ctx, l, bun, pivot, bun->instruction_count);
-}
-
 static void
 mir_compute_interference(
                 compiler_context *ctx,
@@ -428,9 +365,6 @@ mir_compute_interference(
                         mir_liveness_ins_update(live, ins, ctx->temp_count);
                 }
 
-                mir_foreach_bundle_in_block(blk, bun)
-                        mir_compute_bundle_interference(ctx, l, bun);
-
                 free(live);
         }
 }