Mesa (master): radv: disable FMASK compression when drawing with GENERAL layout
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Mon Jul 6 13:39:56 UTC 2020
Module: Mesa
Branch: master
Commit: 7b21ce401f7e81deca5ab6a4353b1369d059bcee
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b21ce401f7e81deca5ab6a4353b1369d059bcee
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Tue Dec 3 14:01:28 2019 +0100
radv: disable FMASK compression when drawing with GENERAL layout
Fixes: 96063100 "radv: enable shaderStorageImageMultisample feature on GFX8+"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3219
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/855
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3165>
---
src/amd/vulkan/radv_cmd_buffer.c | 20 ++++++++++++++++++++
src/amd/vulkan/radv_meta.h | 19 +++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7b0afef9c90..695aa257c31 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1360,6 +1360,13 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
cb_color_info &= C_028C70_DCC_ENABLE;
}
+ if (!radv_layout_can_fast_clear(image, layout, in_render_loop,
+ radv_image_queue_family_mask(image,
+ cmd_buffer->queue_family_index,
+ cmd_buffer->queue_family_index))) {
+ cb_color_info &= C_028C70_COMPRESSION;
+ }
+
if (radv_image_is_tc_compat_cmask(image) &&
(radv_is_fmask_decompress_pipeline(cmd_buffer) ||
radv_is_dcc_decompress_pipeline(cmd_buffer))) {
@@ -1369,6 +1376,19 @@ radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer,
cb_color_info &= C_028C70_FMASK_COMPRESS_1FRAG_ONLY;
}
+ if (radv_image_has_fmask(image) &&
+ (radv_is_fmask_decompress_pipeline(cmd_buffer) ||
+ radv_is_hw_resolve_pipeline(cmd_buffer))) {
+ /* Make sure FMASK is enabled if it has been cleared because:
+ *
+ * 1) it's required for FMASK_DECOMPRESS operations to avoid
+ * GPU hangs
+ * 2) it's necessary for CB_RESOLVE which can read compressed
+ * FMASK data anyways.
+ */
+ cb_color_info |= S_028C70_COMPRESSION(1);
+ }
+
if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);
radeon_emit(cmd_buffer->cs, cb->cb_color_base);
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index f7b19477265..e3711aa4793 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -250,6 +250,25 @@ radv_is_dcc_decompress_pipeline(struct radv_cmd_buffer *cmd_buffer)
meta_state->fast_clear_flush.dcc_decompress_pipeline;
}
+/**
+ * Return whether the bound pipeline is the hardware resolve path.
+ */
+static inline bool
+radv_is_hw_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer)
+{
+ struct radv_meta_state *meta_state = &cmd_buffer->device->meta_state;
+ struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
+
+ for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) {
+ VkFormat format = radv_fs_key_format_exemplars[i];
+ unsigned fs_key = radv_format_meta_fs_key(format);
+
+ if (radv_pipeline_to_handle(pipeline) == meta_state->resolve.pipeline[fs_key])
+ return true;
+ }
+ return false;
+}
+
/* common nir builder helpers */
#include "nir/nir_builder.h"
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