Mesa (master): radeonsi: enable preemption if the kernel enabled it

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 89d2dac55486464832552dfc3349054c29a82922
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=89d2dac55486464832552dfc3349054c29a82922

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Thu Jun 18 01:07:04 2020 -0400

radeonsi: enable preemption if the kernel enabled it

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

---

 src/amd/common/ac_gpu_info.c                       | 3 +++
 src/amd/common/ac_gpu_info.h                       | 2 ++
 src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c | 3 ++-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index fbaa7657b2c..4054e1506a9 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -502,6 +502,8 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 	info->has_2d_tiling = true;
 	info->has_read_registers_query = true;
 	info->has_scheduled_fence_dependency = info->drm_minor >= 28;
+	info->mid_command_buffer_preemption_enabled =
+		amdinfo->ids_flags & AMDGPU_IDS_FLAGS_PREEMPTION;
 
 	info->pa_sc_tile_steering_override = device_info.pa_sc_tile_steering_override;
 	info->num_render_backends = amdinfo->rb_pipes;
@@ -939,6 +941,7 @@ void ac_print_gpu_info(struct radeon_info *info)
 	printf("    has_read_registers_query = %u\n", info->has_read_registers_query);
 	printf("    has_gds_ordered_append = %u\n", info->has_gds_ordered_append);
 	printf("    has_scheduled_fence_dependency = %u\n", info->has_scheduled_fence_dependency);
+	printf("    mid_command_buffer_preemption_enabled = %u\n", info->mid_command_buffer_preemption_enabled);
 
 	printf("Shader core info:\n");
 	printf("    max_shader_clock = %i\n", info->max_shader_clock);
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index 6022a199065..4b2c35c466c 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -152,6 +152,8 @@ struct radeon_info {
 	bool                        has_read_registers_query;
 	bool                        has_gds_ordered_append;
 	bool                        has_scheduled_fence_dependency;
+	/* Whether SR-IOV is enabled or amdgpu.mcbp=1 was set on the kernel command line. */
+	bool                        mid_command_buffer_preemption_enabled;
 
 	/* Shader cores. */
 	uint32_t                    cu_mask[4][2];
diff --git a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
index 84e4ced02e5..bc8f89cacab 100644
--- a/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
+++ b/src/gallium/drivers/radeonsi/si_cp_reg_shadowing.c
@@ -146,7 +146,8 @@ si_create_shadowing_ib_preamble(struct si_context *sctx)
 
 void si_init_cp_reg_shadowing(struct si_context *sctx)
 {
-   if (sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
+   if (sctx->screen->info.mid_command_buffer_preemption_enabled ||
+       sctx->screen->debug_flags & DBG(SHADOW_REGS)) {
       sctx->shadowed_regs =
             si_aligned_buffer_create(sctx->b.screen,
                                      SI_RESOURCE_FLAG_UNMAPPABLE,