Mesa (master): radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING

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Module: Mesa
Branch: master
Commit: 1c6eca23fdd8bc112c70914100601d0e382a8154
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c6eca23fdd8bc112c70914100601d0e382a8154

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Jul  6 23:51:25 2020 -0400

radeonsi/gfx10: set the correct value for OFFCHIP_BUFFERING

Copied from PAL. Higher values break tessellation, which I was only able
to reproduce with register shadowing enabled.

Fixes: 0bf3e6fae7f82b4f16fbcbb05a1ae47f7930e189 "radeonsi/gfx10: double the number of tessellation offchip buffers per SE"

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5798>

---

 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c
index 46f2ff72492..9501cb7c123 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1081,7 +1081,7 @@ static struct pipe_screen *radeonsi_screen_create_impl(struct radeon_winsys *ws,
    unsigned max_offchip_buffers_per_se;
 
    if (sscreen->info.chip_class >= GFX10)
-      max_offchip_buffers_per_se = 256;
+      max_offchip_buffers_per_se = 128;
    /* Only certain chips can use the maximum value. */
    else if (sscreen->info.family == CHIP_VEGA12 || sscreen->info.family == CHIP_VEGA20)
       max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;