Mesa (master): nir/lower_io: Add support for global scratch addressing

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Module: Mesa
Branch: master
Commit: c30824adc07e45e43899b53325049bb006bf8ed5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c30824adc07e45e43899b53325049bb006bf8ed5

Author: Jason Ekstrand <jason at jlekstrand.net>
Date:   Tue Jul 14 13:32:19 2020 -0500

nir/lower_io: Add support for global scratch addressing

This provides an alternate lowering for scratch in which it uses global
reads/writes and bases scratch addresses on a base pointer.

Reviewed-by: Jesse Natalie <jenatali at microsoft.com>
Reviewed-by: Eric Anholt <eric at anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5927>

---

 src/compiler/nir/nir_intrinsics.py |  3 +++
 src/compiler/nir/nir_lower_io.c    | 30 ++++++++++++++++++++++++------
 2 files changed, 27 insertions(+), 6 deletions(-)

diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 2b7614ea353..2fa092d5f71 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -608,6 +608,9 @@ system_value("global_invocation_index", 1, bit_sizes=[32, 64])
 system_value("work_dim", 1)
 system_value("line_width", 1)
 system_value("aa_line_width", 1)
+# BASE=0 for global/shader, BASE=1 for local/function
+system_value("scratch_base_ptr", 0, bit_sizes=[32,64], indices=[BASE])
+
 # Driver-specific viewport scale/offset parameters.
 #
 # VC4 and V3D need to emit a scaled version of the position in the vertex
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 8018bab9cd0..7e328e7ae55 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -854,8 +854,12 @@ build_explicit_io_load(nir_builder *b, nir_intrinsic_instr *intrin,
       break;
    case nir_var_shader_temp:
    case nir_var_function_temp:
-      assert(addr_format_is_offset(addr_format));
-      op = nir_intrinsic_load_scratch;
+      if (addr_format_is_offset(addr_format)) {
+         op = nir_intrinsic_load_scratch;
+      } else {
+         assert(addr_format_is_global(addr_format));
+         op = nir_intrinsic_load_global;
+      }
       break;
    default:
       unreachable("Unsupported explicit IO variable mode");
@@ -956,8 +960,12 @@ build_explicit_io_store(nir_builder *b, nir_intrinsic_instr *intrin,
       break;
    case nir_var_shader_temp:
    case nir_var_function_temp:
-      assert(addr_format_is_offset(addr_format));
-      op = nir_intrinsic_store_scratch;
+      if (addr_format_is_offset(addr_format)) {
+         op = nir_intrinsic_store_scratch;
+      } else {
+         assert(addr_format_is_global(addr_format));
+         op = nir_intrinsic_store_global;
+      }
       break;
    default:
       unreachable("Unsupported explicit IO variable mode");
@@ -1100,8 +1108,18 @@ nir_explicit_io_address_from_deref(nir_builder *b, nir_deref_instr *deref,
    case nir_deref_type_var:
       assert(deref->mode & (nir_var_shader_in | nir_var_mem_shared |
                             nir_var_shader_temp | nir_var_function_temp));
-      return nir_imm_intN_t(b, deref->var->data.driver_location,
-                            deref->dest.ssa.bit_size);
+      if (addr_format_is_global(addr_format)) {
+         assert(nir_var_shader_temp | nir_var_function_temp);
+         base_addr =
+            nir_load_scratch_base_ptr(b, !(deref->mode & nir_var_shader_temp),
+                                      nir_address_format_num_components(addr_format),
+                                      nir_address_format_bit_size(addr_format));
+         return build_addr_iadd_imm(b, base_addr, addr_format,
+                                       deref->var->data.driver_location);
+      } else {
+         return nir_imm_intN_t(b, deref->var->data.driver_location,
+                               deref->dest.ssa.bit_size);
+      }
 
    case nir_deref_type_array: {
       nir_deref_instr *parent = nir_deref_instr_parent(deref);