Mesa (master): amd: add support for Navy Flounder

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Module: Mesa
Branch: master
Commit: abed921ce710d3a4463e0f8ccca2cfadf113e42b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=abed921ce710d3a4463e0f8ccca2cfadf113e42b

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Mon Jul 27 19:13:51 2020 -0400

amd: add support for Navy Flounder

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Acked-by: Leo Liu <leo.liu at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6100>

---

 src/amd/addrlib/src/amdgpu_asic_addr.h      | 2 ++
 src/amd/addrlib/src/gfx10/gfx10addrlib.cpp  | 6 ++++++
 src/amd/common/ac_gpu_info.c                | 2 ++
 src/amd/common/amd_family.h                 | 1 +
 src/amd/llvm/ac_llvm_util.c                 | 1 +
 src/gallium/drivers/radeon/radeon_vcn_dec.c | 1 +
 6 files changed, 13 insertions(+)

diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h b/src/amd/addrlib/src/amdgpu_asic_addr.h
index 5f7d797f2c8..bef2ef78575 100644
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -98,6 +98,7 @@
 #define AMDGPU_NAVI12_RANGE     0x0A, 0x14
 #define AMDGPU_NAVI14_RANGE     0x14, 0x28
 #define AMDGPU_SIENNA_CICHLID_RANGE     0x28, 0x32
+#define AMDGPU_NAVY_FLOUNDER_RANGE      0x32, 0x3C
 
 #define AMDGPU_EXPAND_FIX(x) x
 #define AMDGPU_RANGE_HELPER(val, min, max) ((val >= min) && (val < max))
@@ -146,5 +147,6 @@
 #define ASICREV_IS_NAVI12(r)           ASICREV_IS(r, NAVI12)
 #define ASICREV_IS_NAVI14(r)           ASICREV_IS(r, NAVI14)
 #define ASICREV_IS_SIENNA_CICHLID(r)   ASICREV_IS(r, SIENNA_CICHLID)
+#define ASICREV_IS_NAVY_FLOUNDER(r)    ASICREV_IS(r, NAVY_FLOUNDER)
 
 #endif // _AMDGPU_ASIC_ADDR_H
diff --git a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
index 2050cf4b150..8116c3b169c 100644
--- a/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
+++ b/src/amd/addrlib/src/gfx10/gfx10addrlib.cpp
@@ -927,6 +927,12 @@ ChipFamily Gfx10Lib::HwlConvertChipFamily(
                 m_settings.supportRbPlus   = 1;
                 m_settings.dccUnsup3DSwDis = 0;
             }
+
+            if (ASICREV_IS_NAVY_FLOUNDER(chipRevision))
+            {
+                m_settings.supportRbPlus   = 1;
+                m_settings.dccUnsup3DSwDis = 0;
+            }
             break;
         default:
             ADDR_ASSERT(!"Unknown chip family");
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index f054edba1ce..a5fd949ac06 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -410,6 +410,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 		identify_chip(NAVI12);
 		identify_chip(NAVI14);
 		identify_chip(SIENNA_CICHLID);
+		identify_chip(NAVY_FLOUNDER);
 		break;
 	}
 
@@ -742,6 +743,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 		case CHIP_NAVI10:
 		case CHIP_NAVI12:
 		case CHIP_SIENNA_CICHLID:
+		case CHIP_NAVY_FLOUNDER:
 			pc_lines = 1024;
 			break;
 		case CHIP_NAVI14:
diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 7f581c4945a..485ae276306 100644
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -103,6 +103,7 @@ enum radeon_family {
     CHIP_NAVI12,
     CHIP_NAVI14,
     CHIP_SIENNA_CICHLID,
+    CHIP_NAVY_FLOUNDER,
     CHIP_LAST,
 };
 
diff --git a/src/amd/llvm/ac_llvm_util.c b/src/amd/llvm/ac_llvm_util.c
index 8edef9c3522..29f9352b886 100644
--- a/src/amd/llvm/ac_llvm_util.c
+++ b/src/amd/llvm/ac_llvm_util.c
@@ -157,6 +157,7 @@ const char *ac_get_llvm_processor_name(enum radeon_family family)
 	case CHIP_NAVI14:
 		return "gfx1012";
 	case CHIP_SIENNA_CICHLID:
+	case CHIP_NAVY_FLOUNDER:
 		return "gfx1030";
 	default:
 		return "";
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 038546f56d4..8ef797e6809 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1590,6 +1590,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
       break;
    case CHIP_ARCTURUS:
    case CHIP_SIENNA_CICHLID:
+   case CHIP_NAVY_FLOUNDER:
       dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
       dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
       dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;