Mesa (master): freedreno/registers/a4xx: fix validation error

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Module: Mesa
Branch: master
Commit: c61ad1f542edbbae6484099ac02a9c9bf803ab5f
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=c61ad1f542edbbae6484099ac02a9c9bf803ab5f

Author: Rob Clark <robdclark at chromium.org>
Date:   Tue Jul 28 10:10:14 2020 -0700

freedreno/registers/a4xx: fix validation error

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6107>

---

 src/freedreno/registers/adreno/a4xx.xml | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/freedreno/registers/adreno/a4xx.xml b/src/freedreno/registers/adreno/a4xx.xml
index b4c42538b7f..94c795cec78 100644
--- a/src/freedreno/registers/adreno/a4xx.xml
+++ b/src/freedreno/registers/adreno/a4xx.xml
@@ -1637,7 +1637,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
 	</reg32>
 	<reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
-	<reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>"
+	<reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>
 	<reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
 	<reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
 	<reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
@@ -1652,7 +1652,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
 	</reg32>
 	<reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
-	<reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>"
+	<reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>
 	<reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
 	<reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
 	<reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
@@ -1682,7 +1682,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
 	</reg32>
 	<reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
-	<reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>"
+	<reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>
 	<reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
 	<reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
 
@@ -1716,7 +1716,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
 	</reg32>
 	<reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
-	<reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>"
+	<reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>
 	<reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
 	<reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
 
@@ -1751,7 +1751,7 @@ perhaps they should be taken with a grain of salt
 		<bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
 	</reg32>
 	<reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
-	<reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>"
+	<reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>
 	<reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
 	<reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>