Mesa (master): freedreno/a6xx: Fix CP_BIN_SIZE_ADDRESS name

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Module: Mesa
Branch: master
Commit: 8e626879ddddbea7a68c4b9c9750a178f8b8c006
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e626879ddddbea7a68c4b9c9750a178f8b8c006

Author: Connor Abbott <cwabbott0 at gmail.com>
Date:   Thu Jul 30 12:36:30 2020 +0200

freedreno/a6xx: Fix CP_BIN_SIZE_ADDRESS name

Also document some other registers gleaned from looking at the context
switch save/restore routines and fix CP_SDS_REM_SIZE, and make the names
line up with the CP perfcntr names. Note that the CP reads the draw
stream size in CP_SET_BIN_DATA5 using MEM_READ_ADDR, which is probably
why this was mistaken for the draw stream size address.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6123>

---

 src/freedreno/.gitlab-ci/reference/crash.log | 18 +++++++++---------
 src/freedreno/registers/adreno/a6xx.xml      | 22 +++++++++++++++++-----
 2 files changed, 26 insertions(+), 14 deletions(-)

diff --git a/src/freedreno/.gitlab-ci/reference/crash.log b/src/freedreno/.gitlab-ci/reference/crash.log
index b1a79865cf3..7f17459bf63 100644
--- a/src/freedreno/.gitlab-ci/reference/crash.log
+++ b/src/freedreno/.gitlab-ci/reference/crash.log
@@ -743,12 +743,12 @@ registers:
 	00000000	CP_IB2_REM_SIZE: 0
 	00000000	CP_SDS_BASE: 0
 	00000000	CP_SDS_BASE_HI: 0
-	00000000	0x930: 00000000
-	0000c600	CP_BIN_SIZE_ADDRESS: 0xc600
-	00010000	CP_BIN_SIZE_ADDRESS_HI: 0x10000
-	00000000	0x933: 00000000
-	00000000	CP_BIN_DATA_ADDR: 0
-	00000000	CP_BIN_DATA_ADDR_HI: 0
+	00000000	CP_SDS_REM_SIZE: 0
+	0000c600	CP_MRB_BASE: 0xc600
+	00010000	CP_MRB_BASE_HI: 0x10000
+	00000000	CP_MRB_REM_SIZE: 0
+	00000000	CP_VSD_BASE: 0
+	00000000	CP_VSD_BASE_HI: 0
 	00000000	0x936: 00000000
 	00800000	0x937: 00800000
 	00000000	0x938: 00000000
@@ -762,13 +762,13 @@ registers:
 	0000000c	0x943: 0000000c
 	00000000	0x944: 00000000
 	00000000	0x945: 00000000
-	00000000	0x946: 00000000
-	00000000	0x947: 00000000
+	00000000	CP_MRB_DWORDS: 0
+	00000000	CP_VSD_DWORDS: 0
 	000f0004	0x948: 000f0004
 	00060002	CP_CSQ_IB1_STAT: { REM = 0x6 | 0x2 }
 	00000000	CP_CSQ_IB2_STAT: { REM = 0 }
 	00000000	0x94b: 00000000
-	00000000	0x94c: 00000000
+	00000000	CP_MRQ_MRB_STAT: { REM = 0 }
 	00000000	0x94d: 00000000
 	00305efe	CP_ALWAYS_ON_COUNTER_LO: 0x305efe
 	00000000	CP_ALWAYS_ON_COUNTER_HI: 0
diff --git a/src/freedreno/registers/adreno/a6xx.xml b/src/freedreno/registers/adreno/a6xx.xml
index 1e7eefb1bef..559f253f3a0 100644
--- a/src/freedreno/registers/adreno/a6xx.xml
+++ b/src/freedreno/registers/adreno/a6xx.xml
@@ -1073,11 +1073,19 @@ to upconvert to 32b float internally?
 	<!-- SDS == CP_SET_DRAW_STATE: -->
 	<reg32 offset="0x092e" name="CP_SDS_BASE"/>
 	<reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
-	<reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
-	<reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
-	<reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
-	<reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
-	<reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
+	<reg32 offset="0x0930" name="CP_SDS_REM_SIZE"/>
+	<!-- MRB == MEM_READ_ADDR/$addr in SQE firmware -->
+	<reg32 offset="0x0931" name="CP_MRB_BASE"/>
+	<reg32 offset="0x0932" name="CP_MRB_BASE_HI"/>
+	<reg32 offset="0x0933" name="CP_MRB_REM_SIZE"/>
+	<!--
+	VSD == Visibility Stream Decode
+	This is used by CP to read the draw stream and skip empty draws
+	-->
+	<reg32 offset="0x0934" name="CP_VSD_BASE"/>
+	<reg32 offset="0x0935" name="CP_VSD_BASE_HI"/>
+	<reg32 offset="0x0946" name="CP_MRB_DWORDS"/>
+	<reg32 offset="0x0947" name="CP_VSD_DWORDS"/>
 	<!--
 	There are probably similar registers for RB and SDS, teasing out SDS will
 	take a slightly better test case..
@@ -1090,6 +1098,10 @@ to upconvert to 32b float internally?
 		<doc>number of remaining dwords incl current dword being consumed?</doc>
 		<bitfield name="REM" low="16" high="31"/>
 	</reg32>
+	<reg32 offset="0x094c" name="CP_MRQ_MRB_STAT">
+		<doc>number of dwords that have already been read but haven't been consumed by $addr</doc>
+		<bitfield name="REM" low="16" high="31"/>
+	</reg32>
 	<reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
 	<reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
 	<reg32 offset="0x098D" name="CP_AHB_CNTL"/>