Mesa (master): intel/tools: Manually set ARF register file/nr/subnr

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Module: Mesa
Branch: master
Commit: 90c18ec8db8bed6e1a12ce0a5209c5d4ff1abf99
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=90c18ec8db8bed6e1a12ce0a5209c5d4ff1abf99

Author: Matt Turner <mattst88 at gmail.com>
Date:   Wed Jul 15 22:21:09 2020 -0700

intel/tools: Manually set ARF register file/nr/subnr

brw_reg::subnr is in bytes, like the subnr field in the instruction
word, but we disassemble the subregister number in units of the type.
For example g0.3<1>F would have a subnr=12.

These non-terminals produce a brw_reg and feed into other non-terminals
that call brw_reg(), where they are passed the subnr that we set here.
brw_reg()'s subnr parameter is expected to be in terms of the register
type, and it is multiplied by the type size to calculate the subnr in
bytes.

In these non-terminals, we don't know the register type yet, so we
must store the subregister number as it was given to us in the .subnr
field and let the brw_reg() constructor handle the conversion to the
canonical byte-based subnr form when it knows the type.

Before this patch, subregister numbers applied to these registers would
be multiplied with the type size twice.

Reviewed-by: Sagar Ghuge <sagar.ghuge at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5956>

---

 src/intel/tools/i965_gram.y | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/src/intel/tools/i965_gram.y b/src/intel/tools/i965_gram.y
index 44a25018c56..d2cb05cfb9b 100644
--- a/src/intel/tools/i965_gram.y
+++ b/src/intel/tools/i965_gram.y
@@ -1722,7 +1722,8 @@ indirectgenreg:
 directmsgreg:
 	MSGREG subregnum
 	{
-		$$ = brw_message_reg($1);
+		$$.file = BRW_MESSAGE_REGISTER_FILE;
+		$$.nr = $1;
 		$$.subnr = $2;
 	}
 	;
@@ -1799,7 +1800,9 @@ maskreg:
 			error(&@1, "Mask register number %d"
 				   " out of range\n", $1);
 
-		$$ = brw_mask_reg($2);
+		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+		$$.nr = BRW_ARF_MASK;
+		$$.subnr = $2;
 	}
 	;
 
@@ -1815,7 +1818,8 @@ notifyreg:
 			error(&@2, "Notification sub register number %d"
 				   " out of range\n", $2);
 
-		$$ = brw_notification_reg();
+		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+		$$.nr = BRW_ARF_NOTIFICATION_COUNT;
 		$$.subnr = $2;
 	}
 	;
@@ -1844,7 +1848,9 @@ controlreg:
 			error(&@2, "control sub register number %d"
 				   " out of range\n", $2);
 
-		$$ = brw_cr0_reg($2);
+		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+		$$.nr = BRW_ARF_CONTROL;
+		$$.subnr = $2;
 	}
 	;
 
@@ -1859,15 +1865,12 @@ nullreg:
 threadcontrolreg:
 	THREADREG subregnum
 	{
-		if ($1 > 0)
-			error(&@1, "Thread control register number %d"
-				   " out of range\n", $1);
-
 		if ($2 > 7)
 			error(&@2, "Thread control sub register number %d"
 				   " out of range\n", $2);
 
-		$$ = brw_tdr_reg();
+		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+		$$.nr = BRW_ARF_TDR;
 		$$.subnr = $2;
 	}
 	;
@@ -1889,6 +1892,7 @@ performancereg:
 
 		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
 		$$.nr = BRW_ARF_TIMESTAMP;
+		$$.subnr = $2;
 	}
 	;
 
@@ -1899,7 +1903,9 @@ channelenablereg:
 			error(&@1, "Channel enable register number %d"
 				   " out of range\n", $1);
 
-		$$ = brw_mask_reg($2);
+		$$.file = BRW_ARCHITECTURE_REGISTER_FILE;
+		$$.nr = BRW_ARF_MASK;
+		$$.subnr = $2;
 	}
 	;