Mesa (master): ac: rename has_double_rate_fp16 -> has_packed_math_16bit
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Tue Jun 2 20:46:53 UTC 2020
Module: Mesa
Branch: master
Commit: 116ec850125389f82e540c336dfd44ee7103abda
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=116ec850125389f82e540c336dfd44ee7103abda
Author: Marek Olšák <marek.olsak at amd.com>
Date: Sun May 3 19:27:27 2020 -0400
ac: rename has_double_rate_fp16 -> has_packed_math_16bit
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5003>
---
src/amd/common/ac_gpu_info.c | 2 +-
src/amd/common/ac_gpu_info.h | 2 +-
src/amd/vulkan/radv_device.c | 12 ++++++------
src/amd/vulkan/radv_extensions.py | 4 ++--
src/amd/vulkan/radv_shader.c | 2 +-
5 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index f0128dcf0f0..ba129dcee74 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -592,7 +592,7 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->max_se >= 2;
/* Whether chips support double rate packed math instructions. */
- info->has_double_rate_fp16 = info->chip_class >= GFX9;
+ info->has_packed_math_16bit = info->chip_class >= GFX9;
/* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
info->has_load_ctx_reg_pkt = info->chip_class >= GFX9 ||
diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
index f5d7ea9f892..3f33ec5ae32 100644
--- a/src/amd/common/ac_gpu_info.h
+++ b/src/amd/common/ac_gpu_info.h
@@ -66,7 +66,7 @@ struct radeon_info {
bool rbplus_allowed; /* if RB+ is allowed */
bool has_load_ctx_reg_pkt;
bool has_out_of_order_rast;
- bool has_double_rate_fp16;
+ bool has_packed_math_16bit;
bool cpdma_prefetch_writes_memory;
bool has_gfx9_scissor_bug;
bool has_tc_compat_zrange_bug;
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index c4493d01788..37ba40707e7 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -958,7 +958,7 @@ radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
f->storageBuffer16BitAccess = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
f->uniformAndStorageBuffer16BitAccess = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
f->storagePushConstant16 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
- f->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && (LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco);
+ f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || pdevice->use_aco);
f->multiview = true;
f->multiviewGeometryShader = true;
f->multiviewTessellationShader = true;
@@ -982,7 +982,7 @@ radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
f->storagePushConstant8 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
- f->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
+ f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_aco;
f->shaderInt8 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
f->descriptorIndexing = true;
@@ -1564,7 +1564,7 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
/* On AMD hardware, denormals and rounding modes for fp16/fp64 are
* controlled by the same config register.
*/
- if (pdevice->rad_info.has_double_rate_fp16) {
+ if (pdevice->rad_info.has_packed_math_16bit) {
p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
} else {
@@ -1587,10 +1587,10 @@ radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
p->shaderSignedZeroInfNanPreserveFloat32 = true;
p->shaderDenormFlushToZeroFloat16 = false;
- p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
- p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_double_rate_fp16;
+ p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
+ p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
p->shaderRoundingModeRTZFloat16 = false;
- p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
+ p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
p->shaderDenormFlushToZeroFloat64 = false;
p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
diff --git a/src/amd/vulkan/radv_extensions.py b/src/amd/vulkan/radv_extensions.py
index ea955a136fc..ffe1dae8dae 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -165,8 +165,8 @@ EXTENSIONS = [
Extension('VK_AMD_device_coherent_memory', 1, True),
Extension('VK_AMD_draw_indirect_count', 1, True),
Extension('VK_AMD_gcn_shader', 1, True),
- Extension('VK_AMD_gpu_shader_half_float', 1, '!device->use_aco && device->rad_info.has_double_rate_fp16'),
- Extension('VK_AMD_gpu_shader_int16', 1, '!device->use_aco && device->rad_info.has_double_rate_fp16'),
+ Extension('VK_AMD_gpu_shader_half_float', 1, '!device->use_aco && device->rad_info.has_packed_math_16bit'),
+ Extension('VK_AMD_gpu_shader_int16', 1, '!device->use_aco && device->rad_info.has_packed_math_16bit'),
Extension('VK_AMD_memory_overallocation_behavior', 1, True),
# Disable mixed attachment samples on GFX6-GFX7 until the CTS failures have been resolved.
Extension('VK_AMD_mixed_attachment_samples', 1, 'device->rad_info.chip_class >= GFX8'),
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index fb5dc1b0376..b12b9f10d90 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -370,7 +370,7 @@ radv_shader_compile_to_nir(struct radv_device *device,
.device_group = true,
.draw_parameters = true,
.float_controls = true,
- .float16 = device->physical_device->rad_info.has_double_rate_fp16 && !device->physical_device->use_aco,
+ .float16 = device->physical_device->rad_info.has_packed_math_16bit && !device->physical_device->use_aco,
.float64 = true,
.geometry_streams = true,
.image_ms_array = true,
More information about the mesa-commit
mailing list