Mesa (master): pan/mdg: Don't double-replicate blend on T720
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Wed Jun 3 00:45:04 UTC 2020
Module: Mesa
Branch: master
Commit: 7ac617c1172a5031818fdd907579777acf7729b0
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ac617c1172a5031818fdd907579777acf7729b0
Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date: Tue Jun 2 18:12:14 2020 -0400
pan/mdg: Don't double-replicate blend on T720
We already do this unconditionally in NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5305>
---
src/panfrost/midgard/midgard_compile.c | 22 +---------------------
1 file changed, 1 insertion(+), 21 deletions(-)
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 1e20cfc3d4d..5be0ee354e0 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -1719,27 +1719,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
case nir_intrinsic_store_raw_output_pan:
assert (ctx->stage == MESA_SHADER_FRAGMENT);
reg = nir_src_index(ctx, &instr->src[0]);
-
- if (ctx->quirks & MIDGARD_OLD_BLEND) {
- /* Suppose reg = qr0.xyzw. That means 4 8-bit ---> 1 32-bit. So
- * reg = r0.x. We want to splatter. So we can do a 32-bit move
- * of:
- *
- * imov r0.xyzw, r0.xxxx
- */
-
- unsigned expanded = make_compiler_temp(ctx);
-
- midgard_instruction splatter = v_mov(reg, expanded);
-
- for (unsigned c = 0; c < 16; ++c)
- splatter.swizzle[1][c] = 0;
-
- emit_mir_instruction(ctx, splatter);
- emit_fragment_store(ctx, expanded, ctx->blend_rt);
- } else
- emit_fragment_store(ctx, reg, ctx->blend_rt);
-
+ emit_fragment_store(ctx, reg, ctx->blend_rt);
break;
case nir_intrinsic_store_global:
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