Mesa (master): pan/mdg: Handle regular nir_intrinsic_load_output

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 36af05bbdef4e91a1d0616752150ae00ad0dceb5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=36af05bbdef4e91a1d0616752150ae00ad0dceb5

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Mon Jun  1 14:14:33 2020 -0400

pan/mdg: Handle regular nir_intrinsic_load_output

Instead of the vendored version. Only for blend shaders at the moment,
frag shaders fb_fetch has a lot more going on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5285>

---

 src/panfrost/midgard/midgard_compile.c | 39 +++++++++++++++++++---------------
 1 file changed, 22 insertions(+), 17 deletions(-)

diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index 7b9c9d51559..e9e6c15c678 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -134,6 +134,7 @@ M_LOAD(ld_ubo_int4, nir_type_uint32);
 M_LOAD(ld_int4, nir_type_uint32);
 M_STORE(st_int4, nir_type_uint32);
 M_LOAD(ld_color_buffer_32u, nir_type_uint32);
+M_LOAD(ld_color_buffer_as_fp16, nir_type_float16);
 M_STORE(st_vary_32, nir_type_uint32);
 M_LOAD(ld_cubemap_coords, nir_type_uint32);
 M_LOAD(ld_compute_id, nir_type_uint32);
@@ -1600,8 +1601,7 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
 
         /* Reads 128-bit value raw off the tilebuffer during blending, tasty */
 
-        case nir_intrinsic_load_raw_output_pan:
-        case nir_intrinsic_load_output_u8_as_fp16_pan:
+        case nir_intrinsic_load_raw_output_pan: {
                 reg = nir_dest_index(&instr->dest);
                 assert(ctx->is_blend);
 
@@ -1609,30 +1609,35 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
                  * different semantics than T760 and up */
 
                 midgard_instruction ld = m_ld_color_buffer_32u(reg, 0);
-                bool old_blend = ctx->quirks & MIDGARD_OLD_BLEND;
 
-                if (instr->intrinsic == nir_intrinsic_load_output_u8_as_fp16_pan) {
-                        ld.load_store.op = old_blend ?
-                                midgard_op_ld_color_buffer_as_fp16_old :
-                                midgard_op_ld_color_buffer_as_fp16;
+                if (ctx->quirks & MIDGARD_OLD_BLEND) {
+                        ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
+                        ld.load_store.address = 16;
+                        ld.load_store.arg_2 = 0x1E;
+                }
 
-                        for (unsigned c = 4; c < 16; ++c)
-                                ld.swizzle[0][c] = 0;
+                emit_mir_instruction(ctx, ld);
+                break;
+        }
 
-                        ld.dest_type = nir_type_float16;
+        case nir_intrinsic_load_output: {
+                reg = nir_dest_index(&instr->dest);
+                assert(ctx->is_blend);
 
-                        if (old_blend) {
-                                ld.load_store.address = 1;
-                                ld.load_store.arg_2 = 0x1E;
-                        }
-                } else if (old_blend) {
-                        ld.load_store.op = midgard_op_ld_color_buffer_32u_old;
-                        ld.load_store.address = 16;
+                midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
+
+                for (unsigned c = 4; c < 16; ++c)
+                        ld.swizzle[0][c] = 0;
+
+                if (ctx->quirks & MIDGARD_OLD_BLEND) {
+                        ld.load_store.op = midgard_op_ld_color_buffer_as_fp16_old;
+                        ld.load_store.address = 1;
                         ld.load_store.arg_2 = 0x1E;
                 }
 
                 emit_mir_instruction(ctx, ld);
                 break;
+        }
 
         case nir_intrinsic_load_blend_const_color_rgba: {
                 assert(ctx->is_blend);