Mesa (master): radv: Disable HTILE in ac_surface.

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Module: Mesa
Branch: master
Commit: ec671e871886d773e32385f7f62193836ea25e25
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ec671e871886d773e32385f7f62193836ea25e25

Author: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Date:   Sun May 24 14:00:05 2020 +0200

radv: Disable HTILE in ac_surface.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5194>

---

 src/amd/vulkan/radv_image.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index fdb8177abbc..aec65ce0f43 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -257,6 +257,13 @@ radv_use_fmask_for_image(const struct radv_image *image)
 	       image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT;
 }
 
+static inline bool
+radv_use_htile_for_image(const struct radv_image *image)
+{
+	return image->info.levels == 1 &&
+	       image->info.width * image->info.height >= 8 * 8;
+}
+
 static bool
 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
 				   struct radv_image *image)
@@ -472,6 +479,9 @@ radv_init_surface(struct radv_device *device,
 
 	if (is_depth) {
 		surface->flags |= RADEON_SURF_ZBUFFER;
+		if (!radv_use_htile_for_image(image) ||
+		    (device->instance->debug_flags & RADV_DEBUG_NO_HIZ))
+			surface->flags |= RADEON_SURF_NO_HTILE;
 		if (radv_use_tc_compat_htile_for_image(device, pCreateInfo, image_format))
 			surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
 	}
@@ -1303,14 +1313,6 @@ radv_image_can_enable_cmask(struct radv_image *image)
 	       image->info.depth == 1;
 }
 
-static inline bool
-radv_image_can_enable_htile(struct radv_image *image)
-{
-	return radv_image_has_htile(image) &&
-	       image->info.levels == 1 &&
-	       image->info.width * image->info.height >= 8 * 8;
-}
-
 static void radv_image_disable_dcc(struct radv_image *image)
 {
 	for (unsigned i = 0; i < image->plane_count; ++i)
@@ -1395,8 +1397,7 @@ radv_image_create_layout(struct radv_device *device,
 			image->tc_compatible_cmask = true;
 	} else {
 		/* Otherwise, try to enable HTILE for depth surfaces. */
-		if (radv_image_can_enable_htile(image) &&
-		    !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
+		if (radv_image_has_htile(image)) {
 			image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
 			radv_image_alloc_htile(device, image);
 		} else {