Mesa (master): ac/gpu_info, radv: set max_wave64_per_simd to 20 on GFX10

GitLab Mirror gitlab-mirror at kemper.freedesktop.org
Mon Jun 8 10:53:24 UTC 2020


Module: Mesa
Branch: master
Commit: 1234faa7bf1519f575fc7d06b75fc4b249f54a49
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=1234faa7bf1519f575fc7d06b75fc4b249f54a49

Author: Rhys Perry <pendingchaos02 at gmail.com>
Date:   Thu Jun  4 15:03:11 2020 +0100

ac/gpu_info, radv: set max_wave64_per_simd to 20 on GFX10

Fixes RADV max_waves reporting for GFX10

Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5356>

---

 src/amd/common/ac_gpu_info.c                  | 8 ++++++--
 src/amd/vulkan/winsys/null/radv_null_winsys.c | 8 ++++++--
 2 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
index ba129dcee74..c1510c3c4f8 100644
--- a/src/amd/common/ac_gpu_info.c
+++ b/src/amd/common/ac_gpu_info.c
@@ -739,8 +739,12 @@ bool ac_query_gpu_info(int fd, void *dev_p,
 	if (info->chip_class >= GFX10)
 		info->num_sdp_interfaces = device_info.num_tcc_blocks;
 
-	info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
-				    info->family <= CHIP_VEGAM ? 8 : 10;
+	if (info->chip_class >= GFX10)
+		info->max_wave64_per_simd = 20;
+	else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
+		info->max_wave64_per_simd = 8;
+	else
+		info->max_wave64_per_simd = 10;
 
 	/* The number is per SIMD. There is enough SGPRs for the maximum number
 	 * of Wave32, which is double the number for Wave64.
diff --git a/src/amd/vulkan/winsys/null/radv_null_winsys.c b/src/amd/vulkan/winsys/null/radv_null_winsys.c
index fa23ba1d10a..cb9a10d51f9 100644
--- a/src/amd/vulkan/winsys/null/radv_null_winsys.c
+++ b/src/amd/vulkan/winsys/null/radv_null_winsys.c
@@ -101,8 +101,12 @@ static void radv_null_winsys_query_info(struct radeon_winsys *rws,
 	info->pci_id = gpu_info[info->family].pci_id;
 	info->has_syncobj_wait_for_submit = true;
 	info->max_se = 4;
-	info->max_wave64_per_simd = info->family >= CHIP_POLARIS10 &&
-				    info->family <= CHIP_VEGAM ? 8 : 10;
+	if (info->chip_class >= GFX10)
+		info->max_wave64_per_simd = 20;
+	else if (info->family >= CHIP_POLARIS10 && info->family <= CHIP_VEGAM)
+		info->max_wave64_per_simd = 8;
+	else
+		info->max_wave64_per_simd = 10;
 
 	if (info->chip_class >= GFX10)
 		info->num_physical_sgprs_per_simd = 128 * info->max_wave64_per_simd * 2;



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