Mesa (master): pan/mdg: Remove old depth writeout code

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Module: Mesa
Branch: master
Commit: 8f36904bae59429e022c4585b30d552a6a886ac5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f36904bae59429e022c4585b30d552a6a886ac5

Author: Icecream95 <ixn at keemail.me>
Date:   Sat Jun  6 14:59:31 2020 +1200

pan/mdg: Remove old depth writeout code

We need to be able to do color writeout at the same time as depth
writeout. The old code can't do that, so needs to be removed.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5065>

---

 src/panfrost/midgard/midgard_ra.c       | 10 ++--------
 src/panfrost/midgard/midgard_schedule.c | 13 +++++--------
 2 files changed, 7 insertions(+), 16 deletions(-)

diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 9f092b6dd3b..bebd9c7af56 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -604,14 +604,8 @@ allocate_registers(compiler_context *ctx, bool *spilled)
         mir_foreach_instr_global(ctx, ins) {
                 if (!(ins->compact_branch && ins->writeout)) continue;
 
-                if (ins->src[0] < ctx->temp_count) {
-                        if (ins->writeout_depth)
-                                l->solutions[ins->src[0]] = (16 * 1) + COMPONENT_X * 4;
-                        else if (ins->writeout_stencil)
-                                l->solutions[ins->src[0]] = (16 * 1) + COMPONENT_Y * 4;
-                        else
-                                l->solutions[ins->src[0]] = 0;
-                }
+                if (ins->src[0] < ctx->temp_count)
+                        l->solutions[ins->src[0]] = 0;
 
                 if (ins->src[1] < ctx->temp_count)
                         l->solutions[ins->src[1]] = (16 * 1) + COMPONENT_Z * 4;
diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c
index dc127dcea90..f030027d983 100644
--- a/src/panfrost/midgard/midgard_schedule.c
+++ b/src/panfrost/midgard/midgard_schedule.c
@@ -907,7 +907,6 @@ mir_schedule_alu(
         mir_choose_alu(&branch, instructions, worklist, len, &predicate, ALU_ENAB_BR_COMPACT);
         mir_update_worklist(worklist, len, instructions, branch);
         bool writeout = branch && branch->writeout;
-        bool zs_writeout = writeout && (branch->writeout_depth | branch->writeout_stencil);
 
         if (branch && branch->branch.conditional) {
                 midgard_instruction *cond = mir_schedule_condition(ctx, &predicate, worklist, len, instructions, branch);
@@ -948,7 +947,7 @@ mir_schedule_alu(
                 bundle.last_writeout = branch->last_writeout;
         }
 
-        if (writeout && !zs_writeout) {
+        if (writeout) {
                 vadd = ralloc(ctx, midgard_instruction);
                 *vadd = v_mov(~0, make_compiler_temp(ctx));
 
@@ -1004,7 +1003,7 @@ mir_schedule_alu(
 
         if (writeout) {
                 midgard_instruction *stages[] = { sadd, vadd, smul };
-                unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout ? 1 : 0) : branch->src[0];
+                unsigned src = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : branch->src[0];
                 unsigned writeout_mask = 0x0;
                 bool bad_writeout = false;
 
@@ -1020,12 +1019,10 @@ mir_schedule_alu(
                 }
 
                 /* It's possible we'll be able to schedule something into vmul
-                 * to fill r0/r1. Let's peak into the future, trying to schedule
+                 * to fill r0. Let's peak into the future, trying to schedule
                  * vmul specially that way. */
 
-                unsigned full_mask = zs_writeout ?
-                        (1 << (branch->writeout_depth + branch->writeout_stencil)) - 1 :
-                        0xF;
+                unsigned full_mask = 0xF;
 
                 if (!bad_writeout && writeout_mask != full_mask) {
                         predicate.unit = UNIT_VMUL;
@@ -1048,7 +1045,7 @@ mir_schedule_alu(
 
                 /* Finally, add a move if necessary */
                 if (bad_writeout || writeout_mask != full_mask) {
-                        unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(zs_writeout ? 1 : 0) : make_compiler_temp(ctx);
+                        unsigned temp = (branch->src[0] == ~0) ? SSA_FIXED_REGISTER(0) : make_compiler_temp(ctx);
 
                         vmul = ralloc(ctx, midgard_instruction);
                         *vmul = v_mov(src, temp);