Mesa (master): freedreno/ir3: add debug code to print conflicting half-regs

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Module: Mesa
Branch: master
Commit: 4cabc25fa4c89c29e0338f00b20c6e87b087bcc2
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cabc25fa4c89c29e0338f00b20c6e87b087bcc2

Author: Rob Clark <robdclark at chromium.org>
Date:   Thu Jun 11 09:47:05 2020 -0700

freedreno/ir3: add debug code to print conflicting half-regs

I keep re-typing this from time to time when debugging various things.
Which is dumb.

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5431>

---

 src/freedreno/ir3/disasm-a3xx.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/freedreno/ir3/disasm-a3xx.c b/src/freedreno/ir3/disasm-a3xx.c
index d1e77b08913..de8387f3bca 100644
--- a/src/freedreno/ir3/disasm-a3xx.c
+++ b/src/freedreno/ir3/disasm-a3xx.c
@@ -147,6 +147,13 @@ static void print_reg(struct disasm_ctx *ctx, reg_t reg, bool full,
 		fprintf(ctx->out, "p0.%c", component[reg.comp]);
 	} else {
 		fprintf(ctx->out, "%s%c%d.%c", full ? "" : "h", type, reg.num, component[reg.comp]);
+		if (0 && full && !c) {
+			reg_t hr0 = reg;
+			hr0.iim_val *= 2;
+			reg_t hr1 = hr0;
+			hr1.iim_val += 1;
+			fprintf(ctx->out, " (hr%d.%c,hr%d.%c)", hr0.num, component[hr0.comp], hr1.num, component[hr1.comp]);
+		}
 	}
 }