Mesa (master): pan/mdg: Analyze types for 64-bitness in RA

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Module: Mesa
Branch: master
Commit: 5cf5d3cc2d3a16f7faa3dc23e8e122ef3feb1f2c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cf5d3cc2d3a16f7faa3dc23e8e122ef3feb1f2c

Author: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Date:   Fri Jun 12 12:21:11 2020 -0400

pan/mdg: Analyze types for 64-bitness in RA

Instead of reg_mode.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5443>

---

 src/panfrost/midgard/midgard_ra.c | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 88795a777f5..8167340a340 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -435,6 +435,20 @@ mir_compute_interference(
         }
 }
 
+static bool
+mir_is_64(midgard_instruction *ins)
+{
+        if (nir_alu_type_get_type_size(ins->dest_type) == 64)
+                return true;
+
+        mir_foreach_src(ins, v) {
+                if (nir_alu_type_get_type_size(ins->src_types[v]) == 64)
+                        return true;
+        }
+
+        return false;
+}
+
 /* This routine performs the actual register allocation. It should be succeeded
  * by install_registers */
 
@@ -488,7 +502,7 @@ allocate_registers(compiler_context *ctx, bool *spilled)
                  * but once we get RA we shouldn't disrupt this further. Align
                  * sources of 64-bit instructions. */
 
-                if (ins->type == TAG_ALU_4 && ins->alu.reg_mode == midgard_reg_mode_64) {
+                if (ins->type == TAG_ALU_4 && mir_is_64(ins)) {
                         mir_foreach_src(ins, v) {
                                 unsigned s = ins->src[v];