Mesa (master): radv: make sure to set CB_SHADER_MASK correctly for internal CB operations

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Module: Mesa
Branch: master
Commit: b848d88059b17b221e5fa12afe9876862f18623b
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=b848d88059b17b221e5fa12afe9876862f18623b

Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date:   Thu Jun 11 15:39:46 2020 +0200

radv: make sure to set CB_SHADER_MASK correctly for internal CB operations

It should be always set to 0xf.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5427>

---

 src/amd/vulkan/radv_pipeline.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index f6365292f51..76244ecf503 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -5119,6 +5119,17 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
 			blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
 	}
 
+	if (extra &&
+	    (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
+	     extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
+	     extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
+	     extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
+		/* According to the CB spec states, CB_SHADER_MASK should be
+		 * set to enable writes to all four channels of MRT0.
+		 */
+		blend.cb_shader_mask = 0xf;
+	}
+
 	for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
 		if (pipeline->shaders[i]) {
 			pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;