Mesa (master): radeon/vcn: add Sienna to use internal register offset

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Module: Mesa
Branch: master
Commit: 384195b041d077979d66af2a43dbcc800b1b75f9
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=384195b041d077979d66af2a43dbcc800b1b75f9

Author: Leo Liu <leo.liu at amd.com>
Date:   Thu Jun 11 18:40:07 2020 -0400

radeon/vcn: add Sienna to use internal register offset

And re-group them explicitly

Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: James Zhu <James.Zhu at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>

---

 src/gallium/drivers/radeon/radeon_vcn_dec.c | 38 +++++++++++++++++++----------
 1 file changed, 25 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 2cf6376c749..1e83ef3dc7b 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1563,24 +1563,36 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
    }
    si_vid_clear_buffer(context, &dec->sessionctx);
 
-   if (sctx->family == CHIP_ARCTURUS) {
-      dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
-      dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
-      dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
-      dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
-      dec->jpg.direct_reg = true;
-   } else if (sctx->family >= CHIP_NAVI10 || sctx->family == CHIP_RENOIR) {
-      dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
-      dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
-      dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
-      dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
-      dec->jpg.direct_reg = true;
-   } else {
+   switch (sctx->family) {
+   case CHIP_RAVEN:
+   case CHIP_RAVEN2:
       dec->reg.data0 = RDECODE_VCN1_GPCOM_VCPU_DATA0;
       dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
       dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
       dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
       dec->jpg.direct_reg = false;
+      break;
+   case CHIP_NAVI10:
+   case CHIP_NAVI12:
+   case CHIP_NAVI14:
+   case CHIP_RENOIR:
+      dec->reg.data0 = RDECODE_VCN2_GPCOM_VCPU_DATA0;
+      dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
+      dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
+      dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
+      dec->jpg.direct_reg = true;
+      break;
+   case CHIP_ARCTURUS:
+   case CHIP_SIENNA:
+      dec->reg.data0 = RDECODE_VCN2_5_GPCOM_VCPU_DATA0;
+      dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
+      dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
+      dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
+      dec->jpg.direct_reg = true;
+      break;
+   default:
+      RVID_ERR("VCN is not supported.\n");
+      goto error;
    }
 
    map_msg_fb_it_probs_buf(dec);