Mesa (master): radeon/vcn: add vcn 3.0 encode support
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Thu Jun 18 14:22:39 UTC 2020
Module: Mesa
Branch: master
Commit: 9d5d4f9eaac9dd419373e6a660f80aaf2bfbde5b
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d5d4f9eaac9dd419373e6a660f80aaf2bfbde5b
Author: Thong Thai <thong.thai at amd.com>
Date: Thu Jun 11 19:02:27 2020 -0400
radeon/vcn: add vcn 3.0 encode support
Signed-off-by: Thong Thai <thong.thai at amd.com>
Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: James Zhu <James.Zhu at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>
---
src/gallium/drivers/radeon/radeon_vcn_enc.c | 8 +-
src/gallium/drivers/radeon/radeon_vcn_enc.h | 31 +++++++
src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c | 107 ++++++++++++++++++++++++
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
src/gallium/drivers/radeonsi/meson.build | 1 +
5 files changed, 145 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.c b/src/gallium/drivers/radeon/radeon_vcn_enc.c
index 8635f9d52d0..13ac891b34e 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.c
@@ -441,10 +441,12 @@ struct pipe_video_codec *radeon_create_encoder(struct pipe_context *context,
goto error;
}
- if (sscreen->info.family <= CHIP_RAVEN2)
- radeon_enc_1_2_init(enc);
- else
+ if (sscreen->info.family >= CHIP_SIENNA)
+ radeon_enc_3_0_init(enc);
+ else if (sscreen->info.family >= CHIP_RENOIR)
radeon_enc_2_0_init(enc);
+ else
+ radeon_enc_1_2_init(enc);
return &enc->base;
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc.h b/src/gallium/drivers/radeon/radeon_vcn_enc.h
index cf63602966e..a881042833a 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_enc.h
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc.h
@@ -201,6 +201,8 @@ typedef struct rvcn_enc_h264_spec_misc_s {
uint32_t quarter_pel_enabled;
uint32_t profile_idc;
uint32_t level_idc;
+ uint32_t b_picture_enabled;
+ uint32_t weighted_bipred_idc;
} rvcn_enc_h264_spec_misc_t;
typedef struct rvcn_enc_hevc_spec_misc_s {
@@ -260,6 +262,13 @@ typedef struct rvcn_enc_slice_header_s {
} instructions[RENCODE_SLICE_HEADER_TEMPLATE_MAX_NUM_INSTRUCTIONS];
} rvcn_enc_slice_header_t;
+typedef struct rvcn_enc_h264_reference_picture_info_s {
+ unsigned int pic_type;
+ unsigned int is_long_term;
+ unsigned int picture_structure;
+ unsigned int pic_order_cnt;
+} rvcn_enc_h264_reference_picture_info_t;
+
typedef struct rvcn_enc_encode_params_s {
uint32_t pic_type;
uint32_t allowed_max_bitstream_size;
@@ -276,9 +285,15 @@ typedef struct rvcn_enc_encode_params_s {
typedef struct rvcn_enc_h264_encode_params_s {
uint32_t input_picture_structure;
+ uint32_t input_pic_order_cnt;
uint32_t interlaced_mode;
uint32_t reference_picture_structure;
uint32_t reference_picture1_index;
+ rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture0;
+ uint32_t l0_reference_picture1_index;
+ rvcn_enc_h264_reference_picture_info_t picture_info_l0_reference_picture1;
+ uint32_t l1_reference_picture0_index;
+ rvcn_enc_h264_reference_picture_info_t picture_info_l1_reference_picture0;
} rvcn_enc_h264_encode_params_t;
typedef struct rvcn_enc_h264_deblocking_filter_s {
@@ -309,6 +324,20 @@ typedef struct rvcn_enc_reconstructed_picture_s {
uint32_t chroma_offset;
} rvcn_enc_reconstructed_picture_t;
+typedef struct rvcn_enc_pre_encode_input_picture_s {
+ union {
+ struct {
+ uint32_t luma_offset;
+ uint32_t chroma_offset;
+ } yuv;
+ struct {
+ uint32_t red_offset;
+ uint32_t green_offset;
+ uint32_t blue_offset;
+ } rgb;
+ };
+} rvcn_enc_pre_encode_input_picture_t;
+
typedef struct rvcn_enc_encode_context_buffer_s {
uint32_t encode_context_address_hi;
uint32_t encode_context_address_lo;
@@ -539,4 +568,6 @@ void radeon_enc_1_2_init(struct radeon_encoder *enc);
void radeon_enc_2_0_init(struct radeon_encoder *enc);
+void radeon_enc_3_0_init(struct radeon_encoder *enc);
+
#endif // _RADEON_VCN_ENC_H
diff --git a/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c b/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c
new file mode 100644
index 00000000000..a1d5a964a75
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vcn_enc_3_0.c
@@ -0,0 +1,107 @@
+/**************************************************************************
+ *
+ * Copyright 2020 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ **************************************************************************/
+
+#include <stdio.h>
+
+#include "pipe/p_video_codec.h"
+
+#include "util/u_video.h"
+
+#include "si_pipe.h"
+#include "radeon_video.h"
+#include "radeon_vcn_enc.h"
+
+#define RENCODE_FW_INTERFACE_MAJOR_VERSION 0
+#define RENCODE_FW_INTERFACE_MINOR_VERSION 0
+
+static void radeon_enc_spec_misc(struct radeon_encoder *enc)
+{
+ enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0;
+ enc->enc_pic.spec_misc.cabac_enable = 0;
+ enc->enc_pic.spec_misc.cabac_init_idc = 0;
+ enc->enc_pic.spec_misc.half_pel_enabled = 1;
+ enc->enc_pic.spec_misc.quarter_pel_enabled = 1;
+ enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile);
+ enc->enc_pic.spec_misc.level_idc = enc->base.level;
+ enc->enc_pic.spec_misc.b_picture_enabled = 0;
+ enc->enc_pic.spec_misc.weighted_bipred_idc = 0;
+
+ RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.b_picture_enabled);
+ RADEON_ENC_CS(enc->enc_pic.spec_misc.weighted_bipred_idc);
+ RADEON_ENC_END();
+}
+
+static void radeon_enc_encode_params_h264(struct radeon_encoder *enc)
+{
+ enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME;
+ enc->enc_pic.h264_enc_params.input_pic_order_cnt = 0;
+ enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE;
+ enc->enc_pic.h264_enc_params.l0_reference_picture1_index = 0xFFFFFFFF;
+ enc->enc_pic.h264_enc_params.l1_reference_picture0_index= 0xFFFFFFFF;
+
+ RADEON_ENC_BEGIN(enc->cmd.enc_params_h264);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_pic_order_cnt);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_type);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.is_long_term);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.picture_structure);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture0.pic_order_cnt);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l0_reference_picture1_index);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_type);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.is_long_term);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.picture_structure);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l0_reference_picture1.pic_order_cnt);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.l1_reference_picture0_index);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_type);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.is_long_term);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.picture_structure);
+ RADEON_ENC_CS(enc->enc_pic.h264_enc_params.picture_info_l1_reference_picture0.pic_order_cnt);
+ RADEON_ENC_END();
+}
+
+void radeon_enc_3_0_init(struct radeon_encoder *enc)
+{
+ radeon_enc_2_0_init(enc);
+
+ if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) {
+ enc->spec_misc = radeon_enc_spec_misc;
+ enc->encode_params_codec_spec = radeon_enc_encode_params_h264;
+ }
+
+ enc->enc_pic.session_info.interface_version =
+ ((RENCODE_FW_INTERFACE_MAJOR_VERSION << RENCODE_IF_MAJOR_VERSION_SHIFT) |
+ (RENCODE_FW_INTERFACE_MINOR_VERSION << RENCODE_IF_MINOR_VERSION_SHIFT));
+}
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources b/src/gallium/drivers/radeonsi/Makefile.sources
index f34368c1993..13a89d68695 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -61,6 +61,7 @@ C_SOURCES := \
../radeon/radeon_vcn_dec.h \
../radeon/radeon_vcn_enc_1_2.c \
../radeon/radeon_vcn_enc_2_0.c \
+ ../radeon/radeon_vcn_enc_3_0.c \
../radeon/radeon_vcn_enc.c \
../radeon/radeon_vcn_enc.h \
../radeon/radeon_uvd_enc_1_1.c \
diff --git a/src/gallium/drivers/radeonsi/meson.build b/src/gallium/drivers/radeonsi/meson.build
index 1164a97fa9a..b30b857e39c 100644
--- a/src/gallium/drivers/radeonsi/meson.build
+++ b/src/gallium/drivers/radeonsi/meson.build
@@ -74,6 +74,7 @@ files_libradeonsi = files(
'../radeon/radeon_uvd.h',
'../radeon/radeon_vcn_enc_1_2.c',
'../radeon/radeon_vcn_enc_2_0.c',
+ '../radeon/radeon_vcn_enc_3_0.c',
'../radeon/radeon_vcn_enc.c',
'../radeon/radeon_vcn_enc.h',
'../radeon/radeon_vcn_dec_jpeg.c',
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