Mesa (master): radeon/vcn/dec: add db_aligned_height to message buffer

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Module: Mesa
Branch: master
Commit: 946c5c6b7536a3e1350f6d56cf7509d7cd3dd699
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=946c5c6b7536a3e1350f6d56cf7509d7cd3dd699

Author: Leo Liu <leo.liu at amd.com>
Date:   Thu Jun 11 19:27:57 2020 -0400

radeon/vcn/dec: add db_aligned_height to message buffer

This is required for Sienna

Signed-off-by: Leo Liu <leo.liu at amd.com>
Reviewed-by: Boyuan Zhang <boyuan.zhang at amd.com>
Reviewed-by: James Zhu <James.Zhu at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5501>

---

 src/gallium/drivers/radeon/radeon_vcn_dec.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c b/src/gallium/drivers/radeon/radeon_vcn_dec.c
index 1e83ef3dc7b..6bc60061aab 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -824,6 +824,10 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
                        dec->base.width > 32 && dec->stream_type == RDECODE_CODEC_VP9)
                          ? align(dec->base.width, 64)
                          : align(dec->base.width, 32);
+   if (((struct si_screen*)dec->screen)->info.family >= CHIP_SIENNA &&
+       dec->stream_type == RDECODE_CODEC_VP9)
+      decode->db_aligned_height = align(dec->base.height, 64);
+
    decode->db_surf_tile_config = 0;
 
    decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;