Mesa (master): turnip: Offset by component when lowering gl_TessLevel*
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Mon Jun 22 14:58:15 UTC 2020
Module: Mesa
Branch: master
Commit: ff16e72545bdcf26ae02475d90f911d31518928e
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff16e72545bdcf26ae02475d90f911d31518928e
Author: Brian Ho <brian at brkho.com>
Date: Fri Apr 24 08:22:20 2020 -0700
turnip: Offset by component when lowering gl_TessLevel*
lower_tess_ctrl_block assumes that the gl_TessLevel*
intrinsic_store_outputs have already been collapsed into a single
instruction before the tess lowering step:
store_output ... /* base=0 */ /* wrmask=xyzw */ /* component=0 */
store_output ... /* base=1 */ /* wrmask=xy */ /* component=0 */
While this is true in fd because of st_nir_vectorize_io, we don't do
the same lowering in turnip so each tess level component still has
its own store instruction:
store_output ... /* base=0 */ /* wrmask=x */ /* component=0 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=1 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=2 */
store_output ... /* base=0 */ /* wrmask=x */ /* component=3 */
store_output ... /* base=1 */ /* wrmask=x */ /* component=0 */
store_output ... /* base=1 */ /* wrmask=x */ /* component=1 */
This commit adds a component offset to the tess control lowering. An
alternative is to also perform nir_lower_io_to_vector in turnip, but
ir3 seems to generate the same assembly either way and it's nice to
not have a lowering prereq before tess lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5059>
---
src/freedreno/ir3/ir3_nir_lower_tess.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/freedreno/ir3/ir3_nir_lower_tess.c b/src/freedreno/ir3/ir3_nir_lower_tess.c
index 458b29848a0..bdb98f3d935 100644
--- a/src/freedreno/ir3/ir3_nir_lower_tess.c
+++ b/src/freedreno/ir3/ir3_nir_lower_tess.c
@@ -503,9 +503,12 @@ lower_tess_ctrl_block(nir_block *block, nir_builder *b, struct state *state)
b->cursor = nir_before_instr(&intr->instr);
if (levels) {
- for (int i = 0; i < 4; i++)
- if (nir_intrinsic_write_mask(intr) & (1 << i))
- levels[i] = nir_channel(b, intr->src[0].ssa, i);
+ for (int i = 0; i < 4; i++) {
+ if (nir_intrinsic_write_mask(intr) & (1 << i)) {
+ uint32_t component = nir_intrinsic_component(intr);
+ levels[i + component] = nir_channel(b, intr->src[0].ssa, i);
+ }
+ }
nir_instr_remove(&intr->instr);
} else {
nir_ssa_def *address = nir_load_tess_param_base_ir3(b);
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