Mesa (staging/20.1): r600/sfn: Don't set num_components on TESS sysvalue intrinsics
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Mon Jun 22 17:34:49 UTC 2020
Module: Mesa
Branch: staging/20.1
Commit: 51ec16e09217ff77d39e2b35130194d80d46796c
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51ec16e09217ff77d39e2b35130194d80d46796c
Author: Gert Wollny <gert.wollny at collabora.com>
Date: Sat Jun 20 17:01:15 2020 +0200
r600/sfn: Don't set num_components on TESS sysvalue intrinsics
These instructions are not vectorized, and validation rules added for
this with 167fa2887f09
nir/validate: validate intr->num_components
Fixes: 46a3033b43b9b51cae5c60eea39e7e5af325c4db
r600/sfn: Emit some LDS instructions
Signed-off-by: Gert Wollny <gert.wollny at collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5575>
(cherry picked from commit 97318994bcc07f2d5bb8a0a432202e88d5ac1503)
---
.pick_status.json | 2 +-
src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp | 18 +++++++-----------
src/gallium/drivers/r600/sfn/sfn_shader_base.cpp | 2 +-
3 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/.pick_status.json b/.pick_status.json
index a021eaf534c..090f3fb2e63 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -211,7 +211,7 @@
"description": "r600/sfn: Don't set num_components on TESS sysvalue intrinsics",
"nominated": true,
"nomination_type": 1,
- "resolution": 0,
+ "resolution": 1,
"master_sha": null,
"because_sha": "46a3033b43b9b51cae5c60eea39e7e5af325c4db"
},
diff --git a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
index 9346190d4c0..20ab9714229 100644
--- a/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_nir_lower_tess_io.cpp
@@ -27,9 +27,8 @@ static nir_ssa_def *
emit_load_param_base(nir_builder *b, nir_intrinsic_op op)
{
nir_intrinsic_instr *result = nir_intrinsic_instr_create(b->shader, op);
- result->num_components = 4;
- nir_ssa_dest_init(&result->instr, &result->dest,
- result->num_components, 32, NULL);
+ nir_ssa_dest_init(&result->instr, &result->dest,
+ 4, 32, NULL);
nir_builder_instr_insert(b, &result->instr);
return &result->dest.ssa;
}
@@ -155,9 +154,8 @@ static nir_ssa_def *
r600_load_rel_patch_id(nir_builder *b)
{
auto patch_id = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_tcs_rel_patch_id_r600);
- patch_id->num_components = 1;
nir_ssa_dest_init(&patch_id->instr, &patch_id->dest,
- patch_id->num_components, 32, NULL);
+ 1, 32, NULL);
nir_builder_instr_insert(b, &patch_id->instr);
return &patch_id->dest.ssa;
}
@@ -378,9 +376,8 @@ bool r600_append_tcs_TF_emission(nir_shader *shader, enum pipe_prim_type prim_ty
b->cursor = nir_after_cf_list(&f->impl->body);
auto invocation_id = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_invocation_id);
- invocation_id->num_components = 1;
- nir_ssa_dest_init(&invocation_id->instr, &invocation_id->dest,
- invocation_id->num_components, 32, NULL);
+ nir_ssa_dest_init(&invocation_id->instr, &invocation_id->dest,
+ 1, 32, NULL);
nir_builder_instr_insert(b, &invocation_id->instr);
nir_push_if(b, nir_ieq(b, &invocation_id->dest.ssa, nir_imm_int(b, 0)));
@@ -402,9 +399,8 @@ bool r600_append_tcs_TF_emission(nir_shader *shader, enum pipe_prim_type prim_ty
auto tf_out_base = nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_tcs_tess_factor_base_r600);
- tf_out_base->num_components = 1;
- nir_ssa_dest_init(&tf_out_base->instr, &tf_out_base->dest,
- tf_out_base->num_components, 32, NULL);
+ nir_ssa_dest_init(&tf_out_base->instr, &tf_out_base->dest,
+ 1, 32, NULL);
nir_builder_instr_insert(b, &tf_out_base->instr);
auto out_addr0 = nir_build_alu(b, nir_op_umad24,
diff --git a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
index b7f126c4def..1508c4d9460 100644
--- a/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
+++ b/src/gallium/drivers/r600/sfn/sfn_shader_base.cpp
@@ -427,7 +427,7 @@ bool ShaderFromNirProcessor::emit_load_tcs_param_base(nir_intrinsic_instr* instr
PValue src = get_temp_register();
emit_instruction(new AluInstruction(op1_mov, src, Value::zero, {alu_write, alu_last_instr}));
- GPRVector dest = vec_from_nir(instr->dest, instr->num_components);
+ GPRVector dest = vec_from_nir(instr->dest, nir_dest_num_components(instr->dest));
emit_instruction(new FetchTCSIOParam(dest, src, offset));
return true;
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