Mesa (master): intel/isl: Update mocs for DG1
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Mon Jun 22 21:04:12 UTC 2020
Module: Mesa
Branch: master
Commit: 793b40924161130bedb1a4ff746a8790004304d8
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=793b40924161130bedb1a4ff746a8790004304d8
Author: Rafael Antognolli <rafael.antognolli at intel.com>
Date: Tue Nov 5 15:34:53 2019 -0800
intel/isl: Update mocs for DG1
Reviewed-by: Jordan Justen <jordan.l.justen at intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4956>
---
src/intel/isl/isl.c | 19 ++++++++++++++-----
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index f7689d5b867..e9731616bb1 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -99,11 +99,20 @@ static void
isl_device_setup_mocs(struct isl_device *dev)
{
if (dev->info->gen >= 12) {
- /* TODO: Set PTE to MOCS 61 when the kernel is ready */
- /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
- dev->mocs.external = 3 << 1;
- /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
- dev->mocs.internal = 2 << 1;
+ if (dev->info->is_dg1) {
+ /* L3CC=WB */
+ dev->mocs.internal = 5 << 1;
+ /* Displayables on DG1 are free to cache in L3 since L3 is transient
+ * and flushed at bottom of each submission.
+ */
+ dev->mocs.external = 5 << 1;
+ } else {
+ /* TODO: Set PTE to MOCS 61 when the kernel is ready */
+ /* TC=1/LLC Only, LeCC=1/Uncacheable, LRUM=0, L3CC=1/Uncacheable */
+ dev->mocs.external = 3 << 1;
+ /* TC=LLC/eLLC, LeCC=WB, LRUM=3, L3CC=WB */
+ dev->mocs.internal = 2 << 1;
+ }
} else if (dev->info->gen >= 9) {
/* TC=LLC/eLLC, LeCC=PTE, LRUM=3, L3CC=WB */
dev->mocs.external = 1 << 1;
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