Mesa (master): freedreno/ir3/ra: fix pre-color edge case

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Module: Mesa
Branch: master
Commit: 6da06479878a1b2d765c8fbe3c168b7ecbe86795
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=6da06479878a1b2d765c8fbe3c168b7ecbe86795

Author: Rob Clark <robdclark at chromium.org>
Date:   Mon Jun 22 16:18:13 2020 -0700

freedreno/ir3/ra: fix pre-color edge case

Fixes a case where you have something like:

   aVecOutput.z = aScalarInput;

In particular, skipping over things that are not the first component is
wrong.. in the above case the input we need to precolor is the 3rd
component.  But we need to adjust the target register according to the
offset.

Fixes android.hardware.nativehardware.cts.AHardwareBufferNativeTests

Signed-off-by: Rob Clark <robdclark at chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5601>

---

 src/freedreno/ir3/ir3_ra.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/freedreno/ir3/ir3_ra.c b/src/freedreno/ir3/ir3_ra.c
index c92436f8b21..254de0a7b2f 100644
--- a/src/freedreno/ir3/ir3_ra.c
+++ b/src/freedreno/ir3/ir3_ra.c
@@ -1310,13 +1310,6 @@ ra_precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction **precolor, unsigned
 
 			debug_assert(!(instr->regs[0]->flags & (IR3_REG_HALF | IR3_REG_HIGH)));
 
-			/* only consider the first component: */
-			if (id->off > 0)
-				continue;
-
-			if (ctx->scalar_pass && !should_assign(ctx, instr))
-				continue;
-
 			/* 'base' is in scalar (class 0) but we need to map that
 			 * the conflicting register of the appropriate class (ie.
 			 * input could be vec2/vec3/etc)
@@ -1335,6 +1328,9 @@ ra_precolor(struct ir3_ra_ctx *ctx, struct ir3_instruction **precolor, unsigned
 			 *           .. and so on..
 			 */
 			unsigned regid = instr->regs[0]->num;
+			assert(regid >= id->off);
+			regid -= id->off;
+
 			unsigned reg = ctx->set->gpr_to_ra_reg[id->cls][regid];
 			unsigned name = ra_name(ctx, id);
 			ra_set_node_reg(ctx->g, name, reg);