Mesa (master): freedreno/registers: add CP_DRAW_INDIRECT_MULTI
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Thu Jun 25 16:18:57 UTC 2020
Module: Mesa
Branch: master
Commit: 01799b3448ca4e31bb83a79b95e8b7634fa2c8c7
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=01799b3448ca4e31bb83a79b95e8b7634fa2c8c7
Author: Jonathan Marek <jonathan at marek.ca>
Date: Wed Jun 24 15:53:28 2020 -0400
freedreno/registers: add CP_DRAW_INDIRECT_MULTI
Signed-off-by: Jonathan Marek <jonathan at marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
---
src/freedreno/registers/adreno_pm4.xml | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/src/freedreno/registers/adreno_pm4.xml b/src/freedreno/registers/adreno_pm4.xml
index 76ecd1a327a..0832891912c 100644
--- a/src/freedreno/registers/adreno_pm4.xml
+++ b/src/freedreno/registers/adreno_pm4.xml
@@ -306,6 +306,7 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
<value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
<value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
+ <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX"/>
<value name="CP_DRAW_AUTO" value="0x24"/>
<value name="CP_UNKNOWN_19" value="0x19"/>
@@ -775,6 +776,37 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
</stripe>
</domain>
+<domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
+ <enum name="a6xx_draw_indirect_opcode">
+ <value name="INDIRECT_OP_NORMAL" value="0x2"/>
+ <value name="INDIRECT_OP_INDEXED" value="0x4"/>
+ </enum>
+ <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
+ <reg32 offset="1" name="1">
+ <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode"/>
+ <doc>
+ DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
+ be updated for each draw to {draw_id, first_vertex, first_instance, 0}
+ value of 0 disables it
+ </doc>
+ <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
+ </reg32>
+ <reg32 offset="2" name="2">
+ <bitfield name="DRAW_COUNT" low="0" high="31" type="hex"/>
+ </reg32>
+ <doc>for opcode 2: indirect address. for opcode 4: index address</doc>
+ <reg64 offset="3" name="ADDRESS_0" type="address"/>
+ <reg32 offset="5" name="5">
+ <doc>for opcode 2: stride. for opcode 4: max_indices</doc>
+ <bitfield name="PARAM_0" low="0" high="31" type="hex"/>
+ </reg32>
+ <doc>last 3 dwords only for opcode 4</doc>
+ <reg64 offset="6" name="INDIRECT" type="address"/>
+ <reg32 offset="8" name="8">
+ <bitfield name="STRIDE" low="0" high="31" type="hex"/>
+ </reg32>
+</domain>
+
<domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
<array offset="0" name="" stride="3" length="100">
<reg32 offset="0" name="0">
More information about the mesa-commit
mailing list