Mesa (master): intel: Require ISL_AUX_USAGE_STC_CCS for stencil CCS
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Thu Mar 12 18:15:16 UTC 2020
Module: Mesa
Branch: master
Commit: f047e504a51cde0a0789a848e079ab6b7d470d63
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f047e504a51cde0a0789a848e079ab6b7d470d63
Author: Jason Ekstrand <jason at jlekstrand.net>
Date: Tue Mar 10 12:11:43 2020 -0500
intel: Require ISL_AUX_USAGE_STC_CCS for stencil CCS
Reviewed-by: Nanley Chery <nanley.g.chery at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4056>
---
src/intel/blorp/blorp_genX_exec.h | 3 +--
src/intel/isl/isl_emit_depth_stencil.c | 3 ++-
src/intel/isl/isl_surface_state.c | 3 +++
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h
index cc032e6dba8..b3adc6ad41e 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -1805,8 +1805,7 @@ blorp_emit_gen8_hiz_op(struct blorp_batch *batch,
hzp.DepthBufferResolveEnable = params->depth.enabled;
#if GEN_GEN >= 12
if (params->stencil.enabled) {
- assert(params->stencil.aux_usage == ISL_AUX_USAGE_CCS_E ||
- params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
+ assert(params->stencil.aux_usage == ISL_AUX_USAGE_STC_CCS);
hzp.StencilBufferResolveEnable = true;
}
#endif
diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c
index 3921543e1ad..a437805ca61 100644
--- a/src/intel/isl/isl_emit_depth_stencil.c
+++ b/src/intel/isl/isl_emit_depth_stencil.c
@@ -164,8 +164,9 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch,
sb.Depth = sb.RenderTargetViewExtent = info->view->array_len - 1;
sb.SurfLOD = info->view->base_level;
sb.MinimumArrayElement = info->view->base_array_layer;
+ assert(info->stencil_aux_usage == ISL_AUX_USAGE_NONE ||
+ info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS);
sb.StencilCompressionEnable =
- info->stencil_aux_usage == ISL_AUX_USAGE_CCS_E ||
info->stencil_aux_usage == ISL_AUX_USAGE_STC_CCS;
sb.ControlSurfaceEnable = sb.StencilCompressionEnable;
#elif GEN_GEN >= 8 || GEN_IS_HASWELL
diff --git a/src/intel/isl/isl_surface_state.c b/src/intel/isl/isl_surface_state.c
index 0145be160c7..aff8ba5a806 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -587,6 +587,9 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, void *state,
if (isl_surf_usage_is_depth(info->surf->usage))
assert(isl_aux_usage_has_hiz(info->aux_usage));
+ if (isl_surf_usage_is_stencil(info->surf->usage))
+ assert(info->aux_usage == ISL_AUX_USAGE_STC_CCS);
+
if (isl_aux_usage_has_hiz(info->aux_usage)) {
/* For Gen8-10, there are some restrictions around sampling from HiZ.
* The Skylake PRM docs for RENDER_SURFACE_STATE::AuxiliarySurfaceMode
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