Mesa (master): freedreno/ir3: Remove unused half precision shader key flag.
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Fri May 1 16:46:33 UTC 2020
Module: Mesa
Branch: master
Commit: a361567c4607cb1e7d1d440edbf95a1aa87b4d9a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a361567c4607cb1e7d1d440edbf95a1aa87b4d9a
Author: Eric Anholt <eric at anholt.net>
Date: Wed Apr 15 11:34:16 2020 -0700
freedreno/ir3: Remove unused half precision shader key flag.
The code using it was removed in 4af86bd0b933 ("freedreno/ir3: remove
half-precision output")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4562>
---
src/freedreno/ir3/ir3_shader.h | 6 ------
src/gallium/drivers/freedreno/a3xx/fd3_draw.c | 2 --
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 11 -----------
src/gallium/drivers/freedreno/a4xx/fd4_draw.c | 2 --
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c | 8 --------
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c | 1 -
6 files changed, 30 deletions(-)
diff --git a/src/freedreno/ir3/ir3_shader.h b/src/freedreno/ir3/ir3_shader.h
index 0896bd1b185..14f579baf41 100644
--- a/src/freedreno/ir3/ir3_shader.h
+++ b/src/freedreno/ir3/ir3_shader.h
@@ -248,7 +248,6 @@ struct ir3_shader_key {
unsigned sample_shading : 1;
unsigned msaa : 1;
unsigned color_two_side : 1;
- unsigned half_precision : 1;
/* used when shader needs to handle flat varyings (a4xx)
* for front/back color inputs to frag shader:
*/
@@ -331,9 +330,6 @@ ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *las
if (last_key->color_two_side != key->color_two_side)
return true;
- if (last_key->half_precision != key->half_precision)
- return true;
-
if (last_key->rasterflat != key->rasterflat)
return true;
@@ -386,7 +382,6 @@ ir3_normalize_key(struct ir3_shader_key *key, gl_shader_stage type)
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
key->color_two_side = false;
- key->half_precision = false;
key->rasterflat = false;
if (key->has_per_samp) {
key->fsaturate_s = 0;
@@ -402,7 +397,6 @@ ir3_normalize_key(struct ir3_shader_key *key, gl_shader_stage type)
case MESA_SHADER_TESS_CTRL:
case MESA_SHADER_TESS_EVAL:
key->color_two_side = false;
- key->half_precision = false;
key->rasterflat = false;
if (key->has_per_samp) {
key->fsaturate_s = 0;
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
index 99e44db374c..e5485a0a011 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
@@ -126,8 +126,6 @@ fd3_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.color_two_side = ctx->rasterizer->light_twoside,
.vclamp_color = ctx->rasterizer->clamp_vertex_color,
.fclamp_color = ctx->rasterizer->clamp_fragment_color,
- .half_precision = ctx->in_discard_blit &&
- fd_half_precision(&ctx->batch->framebuffer),
.has_per_samp = (fd3_ctx->fsaturate || fd3_ctx->vsaturate),
.vsaturate_s = fd3_ctx->vsaturate_s,
.vsaturate_t = fd3_ctx->vsaturate_t,
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index a0fc1d3f96e..af4c2737389 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -169,9 +169,6 @@ emit_binning_workaround(struct fd_batch *batch)
.debug = &ctx->debug,
.vtx = &ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
- .key = {
- .half_precision = true,
- },
};
OUT_PKT0(ring, REG_A3XX_RB_MODE_CONTROL, 2);
@@ -367,9 +364,6 @@ fd3_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
.debug = &ctx->debug,
.vtx = &ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
- .key = {
- .half_precision = true,
- },
};
int i;
@@ -551,9 +545,6 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
.sprite_coord_enable = 1,
/* NOTE: They all use the same VP, this is for vtx bufs. */
.prog = &ctx->blit_prog[0],
- .key = {
- .half_precision = fd_half_precision(pfb),
- },
};
float x0, y0, x1, y1;
unsigned bin_w = tile->bin_w;
@@ -680,14 +671,12 @@ fd3_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
* components, so half precision is always sufficient.
*/
emit.prog = &ctx->blit_prog[0];
- emit.key.half_precision = true;
} else {
/* Float depth needs special blit shader that writes depth */
if (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT)
emit.prog = &ctx->blit_z;
else
emit.prog = &ctx->blit_zs;
- emit.key.half_precision = false;
}
emit.fs = NULL; /* frag shader changed so clear cache */
fd3_program_emit(ring, &emit, 1, &pfb->zsbuf);
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
index 9c8ef830051..fadc1511e62 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_draw.c
@@ -111,8 +111,6 @@ fd4_draw_vbo(struct fd_context *ctx, const struct pipe_draw_info *info,
.vclamp_color = ctx->rasterizer->clamp_vertex_color,
.fclamp_color = ctx->rasterizer->clamp_fragment_color,
.rasterflat = ctx->rasterizer->flatshade,
- .half_precision = ctx->in_discard_blit &&
- fd_half_precision(&ctx->batch->framebuffer),
.ucp_enables = ctx->rasterizer->clip_plane_enable,
.has_per_samp = (fd4_ctx->fsaturate || fd4_ctx->vsaturate ||
fd4_ctx->fastc_srgb || fd4_ctx->vastc_srgb),
diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
index 57f23a8304f..05915dbb90d 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
@@ -197,9 +197,6 @@ fd4_emit_tile_gmem2mem(struct fd_batch *batch, const struct fd_tile *tile)
.debug = &ctx->debug,
.vtx = &ctx->solid_vbuf_state,
.prog = &ctx->solid_prog,
- .key = {
- .half_precision = true,
- },
};
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
@@ -337,9 +334,6 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
.sprite_coord_enable = 1,
/* NOTE: They all use the same VP, this is for vtx bufs. */
.prog = &ctx->blit_prog[0],
- .key = {
- .half_precision = fd_half_precision(pfb),
- },
.no_decode_srgb = true,
};
unsigned char mrt_comp[A4XX_MAX_RENDER_TARGETS] = {0};
@@ -470,7 +464,6 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
case PIPE_FORMAT_Z32_FLOAT:
emit.prog = (pfb->zsbuf->format == PIPE_FORMAT_Z32_FLOAT) ?
&ctx->blit_z : &ctx->blit_zs;
- emit.key.half_precision = false;
OUT_PKT0(ring, REG_A4XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, A4XX_RB_DEPTH_CONTROL_Z_ENABLE |
@@ -490,7 +483,6 @@ fd4_emit_tile_mem2gmem(struct fd_batch *batch, const struct fd_tile *tile)
* components, so half precision is always sufficient.
*/
emit.prog = &ctx->blit_prog[0];
- emit.key.half_precision = true;
break;
}
emit.fs = NULL; /* frag shader changed so clear cache */
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 6eecee3a68b..7edee3086bf 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -326,7 +326,6 @@ int main(int argc, char **argv)
if (!strcmp(argv[n], "--half-precision")) {
debug_printf(" %s", argv[n]);
- key.half_precision = true;
n++;
continue;
}
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