Mesa (staging/20.0): intel/fs: Update location of Render Target Array Index for gen12

[GitLab Mirror]

Module: Mesa
Branch: staging/20.0
Commit: 2ddc07ee08b312c0152cf7a748dc27726fbec81c
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ddc07ee08b312c0152cf7a748dc27726fbec81c

Author: D Scott Phillips <d.scott.phillips at intel.com>
Date:   Thu Apr 30 17:38:33 2020 +0000

intel/fs: Update location of Render Target Array Index for gen12

Render Target Array Index has moved from R0.0[26:16] to
R1.1[26:16] on gen12.

Fixes dEQP-VK.multiview.input_attachments.*

Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez at riseup.net>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4836>
(cherry picked from commit 7bd15135a6dc105939a3e1c349217e6346dcf729)

---

 .pick_status.json                 |  2 +-
 src/intel/compiler/brw_fs_nir.cpp | 10 +++++++++-
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 5932232e876..ff73080a43e 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -958,7 +958,7 @@
         "description": "intel/fs: Update location of Render Target Array Index for gen12",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp
index 6e9bf55501d..49953e69586 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3252,7 +3252,15 @@ fs_visitor::nir_emit_gs_intrinsic(const fs_builder &bld,
 static fs_reg
 fetch_render_target_array_index(const fs_builder &bld)
 {
-   if (bld.shader->devinfo->gen >= 6) {
+   if (bld.shader->devinfo->gen >= 12) {
+      /* The render target array index is provided in the thread payload as
+       * bits 26:16 of r1.1.
+       */
+      const fs_reg idx = bld.vgrf(BRW_REGISTER_TYPE_UD);
+      bld.AND(idx, brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 3),
+              brw_imm_uw(0x7ff));
+      return idx;
+   } else if (bld.shader->devinfo->gen >= 6) {
       /* The render target array index is provided in the thread payload as
        * bits 26:16 of r0.0.
        */