Mesa (master): anv: increase minUniformBufferOffsetAlignment to 64

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Module: Mesa
Branch: master
Commit: a0de2e0090535bd49b70c52917e7bdab628d354a
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0de2e0090535bd49b70c52917e7bdab628d354a

Author: Arcady Goldmints-Orlov <agoldmints at igalia.com>
Date:   Tue Apr 28 19:46:48 2020 -0500

anv: increase minUniformBufferOffsetAlignment to 64

Acked-by: Jason Ekstrand <jason at jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4904>

---

 src/intel/vulkan/anv_device.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 8b54408eff0..52ce55eeb84 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -1505,8 +1505,10 @@ void anv_GetPhysicalDeviceProperties(
        * case of R32G32B32A32 which is 16 bytes.
        */
       .minTexelBufferOffsetAlignment            = 16,
-      /* We need 16 for UBO block reads to work and 32 for push UBOs */
-      .minUniformBufferOffsetAlignment          = 32,
+      /* We need 16 for UBO block reads to work and 32 for push UBOs.
+       *  However, we use 64 here to avoid cache issues.
+       */
+      .minUniformBufferOffsetAlignment          = 64,
       .minStorageBufferOffsetAlignment          = 4,
       .minTexelOffset                           = -8,
       .maxTexelOffset                           = 7,