Mesa (master): amdgpu/radeon: add secure api

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Module: Mesa
Branch: master
Commit: 977e19d5cfe02227756aa022a7471570aa17edf7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=977e19d5cfe02227756aa022a7471570aa17edf7

Author: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Date:   Fri Dec  6 10:28:10 2019 +0100

amdgpu/radeon: add secure api

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401>

---

 src/gallium/drivers/radeon/radeon_winsys.h        |  7 +++++++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h         |  3 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c     | 21 +++++++++++++++++++++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h     |  1 +
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 17 +++++++++++++++++
 5 files changed, 49 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h b/src/gallium/drivers/radeon/radeon_winsys.h
index f9fb5a58426..27e32ffdfac 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -673,6 +673,13 @@ struct radeon_winsys {
 
    bool (*read_registers)(struct radeon_winsys *ws, unsigned reg_offset, unsigned num_registers,
                           uint32_t *out);
+
+   /**
+    * Secure context
+    */
+   bool (*ws_is_secure)(struct radeon_winsys *ws);
+   bool (*cs_is_secure)(struct radeon_cmdbuf *cs);
+   void (*cs_set_secure)(struct radeon_cmdbuf *cs, bool secure);
 };
 
 static inline bool radeon_emitted(struct radeon_cmdbuf *cs, unsigned num_dw)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 26c14d8ec69..a50257b5b7b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -122,6 +122,9 @@ struct amdgpu_cs_context {
 
    /* the error returned from cs_flush for non-async submissions */
    int                         error_code;
+
+   /* TMZ: will this command be submitted using the TMZ flag */
+   bool secure;
 };
 
 struct amdgpu_cs {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index b6cc0d0fd19..3d81129a334 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -325,6 +325,24 @@ static bool kms_handle_equals(const void *a, const void *b)
    return a == b;
 }
 
+static bool amdgpu_ws_is_secure(struct radeon_winsys *rws)
+{
+   struct amdgpu_winsys *ws = amdgpu_winsys(rws);
+   return ws->secure;
+}
+
+static bool amdgpu_cs_is_secure(struct radeon_cmdbuf *rcs)
+{
+   struct amdgpu_cs *cs = amdgpu_cs(rcs);
+   return cs->csc->secure;
+}
+
+static void amdgpu_cs_set_secure(struct radeon_cmdbuf *rcs, bool secure)
+{
+   struct amdgpu_cs *cs = amdgpu_cs(rcs);
+   cs->csc->secure = secure;
+}
+
 PUBLIC struct radeon_winsys *
 amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
 		     radeon_screen_create_t screen_create)
@@ -485,6 +503,9 @@ amdgpu_winsys_create(int fd, const struct pipe_screen_config *config,
    ws->base.query_value = amdgpu_query_value;
    ws->base.read_registers = amdgpu_read_registers;
    ws->base.pin_threads_to_L3_cache = amdgpu_pin_threads_to_L3_cache;
+   ws->base.ws_is_secure = amdgpu_ws_is_secure;
+   ws->base.cs_is_secure = amdgpu_cs_is_secure;
+   ws->base.cs_set_secure = amdgpu_cs_set_secure;
 
    amdgpu_bo_init_functions(ws);
    amdgpu_cs_init_functions(ws);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 7e677b517ff..d75efb2fd71 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -85,6 +85,7 @@ struct amdgpu_winsys {
    bool debug_all_bos;
    bool reserve_vmid;
    bool zero_all_vram_allocs;
+   bool secure;
 
    /* List of all allocated buffers */
    simple_mtx_t global_bo_list_lock;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 73ef4bea262..a8f3cb3e3bd 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -801,6 +801,20 @@ static void radeon_pin_threads_to_L3_cache(struct radeon_winsys *ws,
    }
 }
 
+static bool radeon_ws_is_secure(struct radeon_winsys* ws)
+{
+    return false;
+}
+
+static bool radeon_cs_is_secure(struct radeon_cmdbuf* cs)
+{
+    return false;
+}
+
+static void radeon_cs_set_secure(struct radeon_cmdbuf* cs, bool enable)
+{
+}
+
 PUBLIC struct radeon_winsys *
 radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
                          radeon_screen_create_t screen_create)
@@ -872,6 +886,9 @@ radeon_drm_winsys_create(int fd, const struct pipe_screen_config *config,
    ws->base.cs_request_feature = radeon_cs_request_feature;
    ws->base.query_value = radeon_query_value;
    ws->base.read_registers = radeon_read_registers;
+    ws->base.ws_is_secure = radeon_ws_is_secure;
+    ws->base.cs_is_secure = radeon_cs_is_secure;
+    ws->base.cs_set_secure = radeon_cs_set_secure;
 
    radeon_drm_bo_init_functions(ws);
    radeon_drm_cs_init_functions(ws);