Mesa (master): radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly
GitLab Mirror
gitlab-mirror at kemper.freedesktop.org
Fri May 15 22:24:22 UTC 2020
Module: Mesa
Branch: master
Commit: b5ac9d18d8f30893aff1e141f89085dab557b7df
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5ac9d18d8f30893aff1e141f89085dab557b7df
Author: Marek Olšák <marek.olsak at amd.com>
Date: Thu May 7 13:46:10 2020 -0400
radeonsi: use vi_dcc_enabled instead of using tex->surface.dcc_offset directly
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>
---
src/gallium/drivers/radeonsi/si_blit.c | 14 ++++++++------
src/gallium/drivers/radeonsi/si_clear.c | 2 +-
src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++++--
src/gallium/drivers/radeonsi/si_state.c | 4 ++--
4 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c b/src/gallium/drivers/radeonsi/si_blit.c
index 12bea9eba31..fada003f6cf 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -433,7 +433,7 @@ static void si_blit_decompress_color(struct si_context *sctx, struct si_texture
assert(sctx->chip_class == GFX8);
custom_blend = sctx->custom_blend_dcc_decompress;
- assert(tex->surface.dcc_offset);
+ assert(vi_dcc_enabled(tex, first_level));
/* disable levels without DCC */
for (int i = first_level; i <= last_level; i++) {
@@ -504,7 +504,8 @@ static void si_decompress_color_texture(struct si_context *sctx, struct si_textu
bool need_fmask_expand)
{
/* CMASK or DCC can be discarded and we can still end up here. */
- if (!tex->cmask_buffer && !tex->surface.fmask_size && !tex->surface.dcc_offset)
+ if (!tex->cmask_buffer && !tex->surface.fmask_size &&
+ !vi_dcc_enabled(tex, first_level))
return;
si_blit_decompress_color(sctx, tex, first_level, last_level, 0,
@@ -561,7 +562,7 @@ static void si_check_render_feedback_texture(struct si_context *sctx, struct si_
{
bool render_feedback = false;
- if (!tex->surface.dcc_offset)
+ if (!vi_dcc_enabled(tex, first_level))
return;
for (unsigned j = 0; j < sctx->framebuffer.state.nr_cbufs; ++j) {
@@ -793,7 +794,8 @@ void si_decompress_subresource(struct pipe_context *ctx, struct pipe_resource *t
si_update_fb_dirtiness_after_rendering(sctx);
si_decompress_depth(sctx, stex, planes, level, level, first_layer, last_layer);
- } else if (stex->surface.fmask_size || stex->cmask_buffer || stex->surface.dcc_offset) {
+ } else if (stex->surface.fmask_size || stex->cmask_buffer ||
+ vi_dcc_enabled(stex, level)) {
/* If we've rendered into the framebuffer and it's a blitting
* source, make sure the decompression pass is invoked
* by dirtying the framebuffer.
@@ -843,7 +845,7 @@ void si_resource_copy_region(struct pipe_context *ctx, struct pipe_resource *dst
if (!util_format_is_compressed(src->format) && !util_format_is_compressed(dst->format) &&
!util_format_is_depth_or_stencil(src->format) && src->nr_samples <= 1 &&
- !sdst->surface.dcc_offset &&
+ !vi_dcc_enabled(sdst, dst_level) &&
!(dst->target != src->target &&
(src->target == PIPE_TEXTURE_1D_ARRAY || dst->target == PIPE_TEXTURE_1D_ARRAY))) {
si_compute_copy_image(sctx, dst, dst_level, src, src_level, dstx, dsty, dstz,
@@ -1190,7 +1192,7 @@ static void si_flush_resource(struct pipe_context *ctx, struct pipe_resource *re
if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
return;
- if (!tex->is_depth && (tex->cmask_buffer || tex->surface.dcc_offset)) {
+ if (!tex->is_depth && (tex->cmask_buffer || vi_dcc_enabled(tex, 0))) {
si_blit_decompress_color(sctx, tex, 0, res->last_level, 0, util_max_layer(res, 0),
tex->dcc_separate_buffer != NULL, false);
diff --git a/src/gallium/drivers/radeonsi/si_clear.c b/src/gallium/drivers/radeonsi/si_clear.c
index e96903d24ef..ced753f023d 100644
--- a/src/gallium/drivers/radeonsi/si_clear.c
+++ b/src/gallium/drivers/radeonsi/si_clear.c
@@ -689,7 +689,7 @@ static void si_clear_render_target(struct pipe_context *ctx, struct pipe_surface
struct si_context *sctx = (struct si_context *)ctx;
struct si_texture *sdst = (struct si_texture *)dst->texture;
- if (dst->texture->nr_samples <= 1 && !sdst->surface.dcc_offset) {
+ if (dst->texture->nr_samples <= 1 && !vi_dcc_enabled(sdst, dst->u.tex.level)) {
si_compute_clear_render_target(ctx, dst, color, dstx, dsty, width, height,
render_condition_enabled);
return;
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c
index 336aa9100ae..ec3b0af3355 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -519,7 +519,8 @@ static void si_set_sampler_view(struct si_context *sctx, unsigned shader, unsign
samplers->needs_color_decompress_mask &= ~(1u << slot);
}
- if (tex->surface.dcc_offset && p_atomic_read(&tex->framebuffers_bound))
+ if (vi_dcc_enabled(tex, view->u.tex.first_level) &&
+ p_atomic_read(&tex->framebuffers_bound))
sctx->need_check_render_feedback = true;
}
@@ -2349,7 +2350,8 @@ static void si_make_texture_handle_resident(struct pipe_context *ctx, uint64_t h
struct si_texture_handle *, tex_handle);
}
- if (tex->surface.dcc_offset && p_atomic_read(&tex->framebuffers_bound))
+ if (vi_dcc_enabled(tex, sview->base.u.tex.first_level) &&
+ p_atomic_read(&tex->framebuffers_bound))
sctx->need_check_render_feedback = true;
si_update_bindless_texture_descriptor(sctx, tex_handle);
diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c
index 19fb5a9cd1b..8e162fe87c6 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3810,7 +3810,7 @@ static void gfx10_make_texture_descriptor(
state[6] = 0;
state[7] = 0;
- if (tex->surface.dcc_offset) {
+ if (vi_dcc_enabled(tex, first_level)) {
state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
S_00A018_MAX_COMPRESSED_BLOCK_SIZE(tex->surface.u.gfx9.dcc.max_compressed_block_size) |
S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
@@ -4071,7 +4071,7 @@ static void si_make_texture_descriptor(struct si_screen *screen, struct si_textu
state[5] |= S_008F24_LAST_ARRAY(last_layer);
}
- if (tex->surface.dcc_offset) {
+ if (vi_dcc_enabled(tex, first_level)) {
state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(screen, pipe_format));
} else {
/* The last dword is unused by hw. The shader uses it to clear
More information about the mesa-commit
mailing list