Mesa (master): radeonsi: disable the L2 cache for most CPU mappings of textures

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Module: Mesa
Branch: master
Commit: 7356144fe42939ecbc01d2066ca6ea5d0f9351a7
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=7356144fe42939ecbc01d2066ca6ea5d0f9351a7

Author: Marek Olšák <marek.olsak at amd.com>
Date:   Wed May  6 14:51:50 2020 -0400

radeonsi: disable the L2 cache for most CPU mappings of textures

for faster blits over PCIe and no need to flush L2

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer at amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935>

---

 src/gallium/drivers/radeonsi/si_buffer.c  |  8 ++++++++
 src/gallium/drivers/radeonsi/si_pipe.h    |  1 +
 src/gallium/drivers/radeonsi/si_texture.c | 18 ++++++++++++++++--
 3 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_buffer.c b/src/gallium/drivers/radeonsi/si_buffer.c
index 72d5b37dcca..a1805ddfc03 100644
--- a/src/gallium/drivers/radeonsi/si_buffer.c
+++ b/src/gallium/drivers/radeonsi/si_buffer.c
@@ -182,6 +182,14 @@ void si_init_resource_fields(struct si_screen *sscreen, struct si_resource *res,
    if (res->b.b.flags & SI_RESOURCE_FLAG_32BIT)
       res->flags |= RADEON_FLAG_32BIT;
 
+   /* For higher throughput and lower latency over PCIe assuming sequential access.
+    * Only CP DMA, SDMA, and optimized compute benefit from this.
+    * GFX8 and older don't support RADEON_FLAG_UNCACHED.
+    */
+   if (sscreen->info.chip_class >= GFX9 &&
+       res->b.b.flags & SI_RESOURCE_FLAG_UNCACHED)
+      res->flags |= RADEON_FLAG_UNCACHED;
+
    /* Set expected VRAM and GART usage for the buffer. */
    res->vram_usage = 0;
    res->gart_usage = 0;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h b/src/gallium/drivers/radeonsi/si_pipe.h
index 9bd7ac1c6cb..746b39161ad 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -122,6 +122,7 @@
    (((x)&0x3) << SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT)
 #define SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(x)                                                    \
    (((x) >> SI_RESOURCE_FLAG_MICRO_TILE_MODE_SHIFT) & 0x3)
+#define SI_RESOURCE_FLAG_UNCACHED          (PIPE_RESOURCE_FLAG_DRV_PRIV << 12)
 
 enum si_clear_code
 {
diff --git a/src/gallium/drivers/radeonsi/si_texture.c b/src/gallium/drivers/radeonsi/si_texture.c
index e0e59aa37f3..f6f108f3ced 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1694,10 +1694,24 @@ static void *si_texture_transfer_map(struct pipe_context *ctx, struct pipe_resou
    if (use_staging_texture) {
       struct pipe_resource resource;
       struct si_texture *staging;
-
       unsigned bo_usage = usage & PIPE_TRANSFER_READ ? PIPE_USAGE_STAGING : PIPE_USAGE_STREAM;
+      unsigned bo_flags = SI_RESOURCE_FLAG_FORCE_LINEAR;
+
+      /* The pixel shader has a bad access pattern for linear textures.
+       * If a pixel shader is used to blit to/from staging, don't disable caches.
+       *
+       * MSAA, depth/stencil textures, and compressed textures use the pixel shader
+       * to blit.
+       */
+      if (texture->nr_samples <= 1 &&
+          !tex->is_depth &&
+          !util_format_is_compressed(texture->format) &&
+          /* Texture uploads with DCC use the pixel shader to blit */
+          (!(usage & PIPE_TRANSFER_WRITE) || !vi_dcc_enabled(tex, level)))
+         bo_flags |= SI_RESOURCE_FLAG_UNCACHED;
+
       si_init_temp_resource_from_box(&resource, texture, box, level, bo_usage,
-                                     SI_RESOURCE_FLAG_FORCE_LINEAR);
+                                     bo_flags);
 
       /* Since depth-stencil textures don't support linear tiling,
        * blit from ZS to color and vice versa. u_blitter will do