Mesa (master): intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMM

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Module: Mesa
Branch: master
Commit: 570bd760d3e1c2754fc045981d2162df67e81592
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=570bd760d3e1c2754fc045981d2162df67e81592

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Sat Apr  4 17:57:11 2020 +0300

intel/genxml: fix bits generation for MI_LOAD_REGISTER_IMM

This instruction has a group with the same name than another field above :

  <field name="Data DWord" start="64" end="95" type="uint"/>
  <group count="0" start="96" size="64">
    <field name="Register Offset" start="2" end="22" type="offset"/>
    <field name="Data DWord" start="32" end="63" type="uint"/>
  </group>

The script was replacing the offset of the field first with the second
one in the group.

This change ignore anything a group within an instruction.

v2: Drop unused variable (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli at intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>

---

 src/intel/genxml/gen_bits_header.py | 20 ++++++++++++--------
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/intel/genxml/gen_bits_header.py b/src/intel/genxml/gen_bits_header.py
index 2bc956f39dd..16252a3bd14 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -247,7 +247,8 @@ class XmlParser(object):
 
         self.gen = None
         self.containers = containers
-        self.container = None
+        self.container_stack = []
+        self.container_stack.append(None)
 
     def parse(self, filename):
         with open(filename, 'rb') as f:
@@ -260,8 +261,11 @@ class XmlParser(object):
             if name == 'instruction' and 'engine' in attrs:
                 engines = set(attrs['engine'].split('|'))
                 if not engines & self.engines:
+                    self.container_stack.append(None)
                     return
             self.start_container(attrs)
+        elif name == 'group':
+            self.container_stack.append(None)
         elif name == 'field':
             self.start_field(attrs)
         else:
@@ -270,28 +274,28 @@ class XmlParser(object):
     def end_element(self, name):
         if name == 'genxml':
             self.gen = None
-        elif name in ('instruction', 'struct', 'register'):
-            self.container = None
+        elif name in ('instruction', 'struct', 'register', 'group'):
+            self.container_stack.pop()
         else:
             pass
 
     def start_container(self, attrs):
-        assert self.container is None
+        assert self.container_stack[-1] is None
         name = attrs['name']
         if name not in self.containers:
             self.containers[name] = Container(name)
-        self.container = self.containers[name]
-        self.container.add_gen(self.gen, attrs)
+        self.container_stack.append(self.containers[name])
+        self.container_stack[-1].add_gen(self.gen, attrs)
 
     def start_field(self, attrs):
-        if self.container is None:
+        if self.container_stack[-1] is None:
             return
 
         field_name = attrs.get('name', None)
         if not field_name:
             return
 
-        self.container.get_field(field_name, True).add_gen(self.gen, attrs)
+        self.container_stack[-1].get_field(field_name, True).add_gen(self.gen, attrs)
 
 def parse_args():
     p = argparse.ArgumentParser()