Mesa (master): intel/perf: reuse offset specified in the query

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: ceb822f9e00f57ebf7fccea4dd8acb510e28cefd
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceb822f9e00f57ebf7fccea4dd8acb510e28cefd

Author: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Date:   Fri Sep 13 17:21:02 2019 +0300

intel/perf: reuse offset specified in the query

The current code relies on the order of the function
gen_perf_query_result_accumulate() to match the descriptions written
by gen_perf.py. Let's just reuse the offset specified in the python
script.

v2: Use accumlator offsets more (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2775>

---

 src/intel/perf/gen_perf.c | 40 ++++++++++++++++++++++++++++------------
 1 file changed, 28 insertions(+), 12 deletions(-)

diff --git a/src/intel/perf/gen_perf.c b/src/intel/perf/gen_perf.c
index 2dc63c5226f..e9ad6dd570f 100644
--- a/src/intel/perf/gen_perf.c
+++ b/src/intel/perf/gen_perf.c
@@ -939,7 +939,7 @@ gen_perf_query_result_accumulate(struct gen_perf_query_result *result,
                                  const uint32_t *start,
                                  const uint32_t *end)
 {
-   int i, idx = 0;
+   int i;
 
    if (result->hw_id == OA_REPORT_INVALID_CTX_ID &&
        start[2] != OA_REPORT_INVALID_CTX_ID)
@@ -950,27 +950,43 @@ gen_perf_query_result_accumulate(struct gen_perf_query_result *result,
 
    switch (query->oa_format) {
    case I915_OA_FORMAT_A32u40_A4u32_B8_C8:
-      accumulate_uint32(start + 1, end + 1, result->accumulator + idx++); /* timestamp */
-      accumulate_uint32(start + 3, end + 3, result->accumulator + idx++); /* clock */
+      accumulate_uint32(start + 1, end + 1,
+                        result->accumulator + query->gpu_time_offset); /* timestamp */
+      accumulate_uint32(start + 3, end + 3,
+                        result->accumulator + query->gpu_clock_offset); /* clock */
 
       /* 32x 40bit A counters... */
-      for (i = 0; i < 32; i++)
-         accumulate_uint40(i, start, end, result->accumulator + idx++);
+      for (i = 0; i < 32; i++) {
+         accumulate_uint40(i, start, end,
+                           result->accumulator + query->a_offset + i);
+      }
 
       /* 4x 32bit A counters... */
-      for (i = 0; i < 4; i++)
-         accumulate_uint32(start + 36 + i, end + 36 + i, result->accumulator + idx++);
+      for (i = 0; i < 4; i++) {
+         accumulate_uint32(start + 36 + i, end + 36 + i,
+                           result->accumulator + query->a_offset + 32 + i);
+      }
+
+      /* 8x 32bit B counters */
+      for (i = 0; i < 8; i++) {
+         accumulate_uint32(start + 48 + i, end + 48 + i,
+                           result->accumulator + query->b_offset + i);
+      }
 
-      /* 8x 32bit B counters + 8x 32bit C counters... */
-      for (i = 0; i < 16; i++)
-         accumulate_uint32(start + 48 + i, end + 48 + i, result->accumulator + idx++);
+      /* 8x 32bit C counters... */
+      for (i = 0; i < 8; i++) {
+         accumulate_uint32(start + 56 + i, end + 56 + i,
+                           result->accumulator + query->c_offset + i);
+      }
       break;
 
    case I915_OA_FORMAT_A45_B8_C8:
       accumulate_uint32(start + 1, end + 1, result->accumulator); /* timestamp */
 
-      for (i = 0; i < 61; i++)
-         accumulate_uint32(start + 3 + i, end + 3 + i, result->accumulator + 1 + i);
+      for (i = 0; i < 61; i++) {
+         accumulate_uint32(start + 3 + i, end + 3 + i,
+                           result->accumulator + query->a_offset + i);
+      }
       break;
 
    default: