Mesa (staging/20.1): anv/gen11+: Disable object level preemption

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Module: Mesa
Branch: staging/20.1
Commit: 831e2d63710fd35e48b64d21f562df9ea264de18
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=831e2d63710fd35e48b64d21f562df9ea264de18

Author: D Scott Phillips <d.scott.phillips at intel.com>
Date:   Tue May 19 13:42:26 2020 -0700

anv/gen11+: Disable object level preemption

An unknown issue is causing vs push constants to become corrupted
during object-level preemption. For now, restrict to command
buffer level preemption to avoid rendering corruption.

Cc: <mesa-stable at lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5110>
(cherry picked from commit 81201e461772a06ed2c20207d2901f6cf9a24114)

---

 .pick_status.json             |  2 +-
 src/intel/vulkan/genX_state.c | 16 ++++++++++++++++
 2 files changed, 17 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index e7f95bccf37..40d4754914e 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1210,7 +1210,7 @@
         "description": "anv/gen11+: Disable object level preemption",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "master_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 84c43473774..69c49a46ad3 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -237,6 +237,22 @@ genX(init_device_state)(struct anv_device *device)
          lri.DataDWord      = cache_mode_0;
       }
    }
+
+   /* an unknown issue is causing vs push constants to become
+    * corrupted during object-level preemption. For now, restrict
+    * to command buffer level preemption to avoid rendering
+    * corruption.
+    */
+   uint32_t cs_chicken1;
+   anv_pack_struct(&cs_chicken1,
+                   GENX(CS_CHICKEN1),
+                   .ReplayMode = MidcmdbufferPreemption,
+                   .ReplayModeMask = true);
+
+   anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
+      lri.RegisterOffset = GENX(CS_CHICKEN1_num);
+      lri.DataDWord      = cs_chicken1;
+   }
 #endif
 
 #if GEN_GEN == 12