Mesa (master): spirv: add ReadClockKHR support with device scope
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Sun May 24 19:42:34 UTC 2020
Module: Mesa
Branch: master
Commit: 37c88c670f79f4833856e9193d3b7696c8b5ad8a
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37c88c670f79f4833856e9193d3b7696c8b5ad8a
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Wed May 20 09:54:50 2020 +0200
spirv: add ReadClockKHR support with device scope
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas at basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5117>
---
src/compiler/glsl/glsl_to_nir.cpp | 1 +
src/compiler/nir/nir_intrinsics.py | 3 ++-
src/compiler/spirv/spirv_to_nir.c | 15 ++++++++++++++-
src/compiler/spirv/vtn_amd.c | 1 +
4 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp
index a6fc2671880..c9e0607271e 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -1379,6 +1379,7 @@ nir_visitor::visit(ir_call *ir)
case nir_intrinsic_shader_clock:
nir_ssa_dest_init(&instr->instr, &instr->dest, 2, 32, NULL);
instr->num_components = 2;
+ nir_intrinsic_set_memory_scope(instr, NIR_SCOPE_SUBGROUP);
nir_builder_instr_insert(&b, &instr->instr);
break;
case nir_intrinsic_begin_invocation_interlock:
diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py
index 393f3fa9be7..1f4005877b3 100644
--- a/src/compiler/nir/nir_intrinsics.py
+++ b/src/compiler/nir/nir_intrinsics.py
@@ -229,7 +229,8 @@ intrinsic("scoped_memory_barrier",
# GLSL intrinsic.
# The latter can be used as code motion barrier, which is currently not
# feasible with NIR.
-intrinsic("shader_clock", dest_comp=2, flags=[CAN_ELIMINATE])
+intrinsic("shader_clock", dest_comp=2, flags=[CAN_ELIMINATE],
+ indices=[MEMORY_SCOPE])
# Shader ballot intrinsics with semantics analogous to the
#
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 6ae1ea81188..fd3f4d01104 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -5012,7 +5012,19 @@ vtn_handle_body_instruction(struct vtn_builder *b, SpvOp opcode,
}
case SpvOpReadClockKHR: {
- assert(vtn_constant_uint(b, w[3]) == SpvScopeSubgroup);
+ SpvScope scope = vtn_constant_uint(b, w[3]);
+ nir_scope nir_scope;
+
+ switch (scope) {
+ case SpvScopeDevice:
+ nir_scope = NIR_SCOPE_DEVICE;
+ break;
+ case SpvScopeSubgroup:
+ nir_scope = NIR_SCOPE_SUBGROUP;
+ break;
+ default:
+ vtn_fail("invalid read clock scope");
+ }
/* Operation supports two result types: uvec2 and uint64_t. The NIR
* intrinsic gives uvec2, so pack the result for the other case.
@@ -5020,6 +5032,7 @@ vtn_handle_body_instruction(struct vtn_builder *b, SpvOp opcode,
nir_intrinsic_instr *intrin =
nir_intrinsic_instr_create(b->nb.shader, nir_intrinsic_shader_clock);
nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
+ nir_intrinsic_set_memory_scope(intrin, nir_scope);
nir_builder_instr_insert(&b->nb, &intrin->instr);
struct vtn_type *type = vtn_value(b, w[1], vtn_value_type_type)->type;
diff --git a/src/compiler/spirv/vtn_amd.c b/src/compiler/spirv/vtn_amd.c
index 195baef9c00..d893bd07a34 100644
--- a/src/compiler/spirv/vtn_amd.c
+++ b/src/compiler/spirv/vtn_amd.c
@@ -46,6 +46,7 @@ vtn_handle_amd_gcn_shader_instruction(struct vtn_builder *b, SpvOp ext_opcode,
nir_intrinsic_instr *intrin = nir_intrinsic_instr_create(b->nb.shader,
nir_intrinsic_shader_clock);
nir_ssa_dest_init(&intrin->instr, &intrin->dest, 2, 32, NULL);
+ nir_intrinsic_set_memory_scope(intrin, NIR_SCOPE_SUBGROUP);
nir_builder_instr_insert(&b->nb, &intrin->instr);
val->ssa->def = nir_pack_64_2x32(&b->nb, &intrin->dest.ssa);
break;
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