Mesa (master): intel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders

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Module: Mesa
Branch: master
Commit: 5b5e77caa7f0225aab3701de66b7434553c66033
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b5e77caa7f0225aab3701de66b7434553c66033

Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date:   Tue May 19 10:08:12 2020 -0700

intel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders

The "no32" flag will have precedence over "do32", like is done for FS.

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

---

 src/intel/compiler/brw_fs.cpp | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 83702ef78b5..83ecef8fa37 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -9063,13 +9063,16 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
       min_dispatch_width = max_dispatch_width = required_dispatch_width;
    }
 
+   assert(min_dispatch_width <= max_dispatch_width);
+
    fs_visitor *v8 = NULL, *v16 = NULL, *v32 = NULL;
    fs_visitor *v = NULL;
    const char *fail_msg = NULL;
 
    /* Now the main event: Visit the shader IR and generate our CS IR for it.
     */
-   if (min_dispatch_width <= 8 && max_dispatch_width >= 8) {
+   if (likely(!(INTEL_DEBUG & DEBUG_NO8)) &&
+       min_dispatch_width <= 8 && max_dispatch_width >= 8) {
       nir_shader *nir8 = compile_cs_to_nir(compiler, mem_ctx, key,
                                            src_shader, 8);
       v8 = new fs_visitor(compiler, log_data, mem_ctx, &key->base,
@@ -9118,7 +9121,8 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
       }
    }
 
-   if ((!v || !v->spilled_any_registers) &&
+   if (likely(!(INTEL_DEBUG & DEBUG_NO32)) &&
+       (!v || !v->spilled_any_registers) &&
        !fail_msg && (min_dispatch_width > 16 || (INTEL_DEBUG & DEBUG_DO32)) &&
        max_dispatch_width >= 32) {
       /* Try a SIMD32 compile */
@@ -9148,6 +9152,17 @@ brw_compile_cs(const struct brw_compiler *compiler, void *log_data,
       }
    }
 
+   if (unlikely(!v && (INTEL_DEBUG & (DEBUG_NO8 | DEBUG_NO16 | DEBUG_NO32)))) {
+      if (error_str) {
+         *error_str =
+            ralloc_strdup(mem_ctx,
+                          "Cannot satisfy INTEL_DEBUG flags SIMD restrictions");
+      }
+      return NULL;
+   }
+
+   assert(v);
+
    const unsigned *ret = NULL;
    if (unlikely(v == NULL)) {
       assert(fail_msg);