Mesa (master): radv,aco: adjust the sample mask only if per-sample shading is enabled
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Mon Nov 2 08:11:47 UTC 2020
Module: Mesa
Branch: master
Commit: c63bcda22c8deaed063e0a950839012b97b041b2
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c63bcda22c8deaed063e0a950839012b97b041b2
Author: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Date: Thu Oct 29 16:39:28 2020 +0100
radv,aco: adjust the sample mask only if per-sample shading is enabled
When per-sample shading isn't enabled, we can just load the
samplemask from the hardware which is always the coverage of
the entire pixel/fragment.
fossilds-db (VEGA10):
Totals from 131 (0.10% of 136546) affected shaders:
SGPRs: 5056 -> 5048 (-0.16%)
VGPRs: 2600 -> 2372 (-8.77%)
CodeSize: 115788 -> 112560 (-2.79%)
MaxWaves: 1266 -> 1274 (+0.63%)
Instrs: 20620 -> 20071 (-2.66%)
Cycles: 82416 -> 80220 (-2.66%)
VMEM: 51567 -> 35532 (-31.10%); split: +0.24%, -31.34%
SMEM: 8952 -> 8258 (-7.75%); split: +0.11%, -7.86%
SClause: 1223 -> 1199 (-1.96%); split: -2.62%, +0.65%
Copies: 1247 -> 1124 (-9.86%); split: -10.18%, +0.32%
PreVGPRs: 2112 -> 1981 (-6.20%)
Helps Britannia, Shadow of the Tomb Raider, Warhammer II and Control.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset at gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof at gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7377>
---
src/amd/compiler/aco_instruction_selection.cpp | 15 ++++++++++-----
src/amd/vulkan/radv_nir_to_llvm.c | 13 +++++++++----
2 files changed, 19 insertions(+), 9 deletions(-)
diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp
index 8c7e3e749b1..a16c9035a30 100644
--- a/src/amd/compiler/aco_instruction_selection.cpp
+++ b/src/amd/compiler/aco_instruction_selection.cpp
@@ -6810,12 +6810,17 @@ void visit_load_sample_mask_in(isel_context *ctx, nir_intrinsic_instr *instr) {
Builder bld(ctx->program, ctx->block);
- Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
- get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
- Temp ps_iter_mask = bld.copy(bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
- Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
Temp dst = get_ssa_temp(ctx, &instr->dest.ssa);
- bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
+
+ if (log2_ps_iter_samples) {
+ Temp sample_id = bld.vop3(aco_opcode::v_bfe_u32, bld.def(v1),
+ get_arg(ctx, ctx->args->ac.ancillary), Operand(8u), Operand(4u));
+ Temp ps_iter_mask = bld.copy(bld.def(v1), Operand(ps_iter_masks[log2_ps_iter_samples]));
+ Temp mask = bld.vop2(aco_opcode::v_lshlrev_b32, bld.def(v1), sample_id, ps_iter_mask);
+ bld.vop2(aco_opcode::v_and_b32, Definition(dst), mask, get_arg(ctx, ctx->args->ac.sample_coverage));
+ } else {
+ bld.copy(Definition(dst), get_arg(ctx, ctx->args->ac.sample_coverage));
+ }
}
unsigned gs_outprim_vertices(unsigned outprim)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c
index 793381bce1b..3025afb2352 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -758,10 +758,15 @@ static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
LLVMValueRef result, sample_id;
- sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
- sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
- result = LLVMBuildAnd(ctx->ac.builder, sample_id,
- ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
+ if (log2_ps_iter_samples) {
+ sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
+ sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
+ result = LLVMBuildAnd(ctx->ac.builder, sample_id,
+ ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
+ } else {
+ result = ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage);
+ }
+
return result;
}
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