Mesa (master): freedreno: Use freedreno_dev_info
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Mon Nov 2 18:18:31 UTC 2020
Module: Mesa
Branch: master
Commit: aa2f6bd4f5688034bb716a50104c93c2881b29d9
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa2f6bd4f5688034bb716a50104c93c2881b29d9
Author: Connor Abbott <cwabbott0 at gmail.com>
Date: Thu Oct 29 11:08:30 2020 +0100
freedreno: Use freedreno_dev_info
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7385>
---
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c | 2 +-
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c | 11 ++--
src/gallium/drivers/freedreno/a6xx/fd6_context.c | 56 ----------------
src/gallium/drivers/freedreno/a6xx/fd6_context.h | 11 ----
src/gallium/drivers/freedreno/a6xx/fd6_draw.c | 7 +-
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c | 28 ++++----
src/gallium/drivers/freedreno/freedreno_gmem.c | 74 ++++------------------
src/gallium/drivers/freedreno/freedreno_gmem.h | 1 -
src/gallium/drivers/freedreno/freedreno_resource.c | 6 +-
src/gallium/drivers/freedreno/freedreno_screen.c | 2 +-
src/gallium/drivers/freedreno/freedreno_screen.h | 7 +-
src/gallium/drivers/freedreno/gmemtool.c | 6 +-
12 files changed, 47 insertions(+), 164 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index f61f5db22a8..8b00de83957 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -572,7 +572,7 @@ fd2_emit_tile_init(struct fd_batch *batch)
if (cf->opc == ALLOC)
cf++;
assert(cf->opc == EXEC);
- assert(cf[ctx->screen->num_vsc_pipes*2-2].opc == EXEC_END);
+ assert(cf[ctx->screen->info.num_vsc_pipes*2-2].opc == EXEC_END);
cf[2*(gmem->num_vsc_pipes-1)].opc = EXEC_END;
}
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
index ac1468e2c0f..c1019dc114a 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
@@ -235,6 +235,7 @@ static void
emit_setup(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->draw;
+ struct fd_screen *screen = batch->ctx->screen;
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
@@ -244,7 +245,7 @@ emit_setup(struct fd_batch *batch)
/* normal BLIT_OP_SCALE operation needs bypass RB_CCU_CNTL */
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
+ OUT_RING(ring, A6XX_RB_CCU_CNTL_OFFSET(screen->info.a6xx.ccu_offset_bypass));
}
static void
@@ -420,7 +421,7 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
+ OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@@ -514,7 +515,7 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_UNKNOWN_8E04_blit);
+ OUT_RING(ring, batch->ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@@ -685,7 +686,7 @@ emit_blit_texture(struct fd_context *ctx,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
+ OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
@@ -776,7 +777,7 @@ fd6_clear_surface(struct fd_context *ctx,
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.RB_UNKNOWN_8E04_blit);
+ OUT_RING(ring, ctx->screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.c b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
index c634c03fbc7..508b6fe0dd4 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_context.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.c
@@ -135,62 +135,6 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags)
if (!fd6_ctx)
return NULL;
-
- switch (screen->gpu_id) {
- case 618:
-/*
-GRAS_BIN_CONTROL:
-RB_BIN_CONTROL:
- - a618 doesn't appear to set .USE_VIZ; also bin size diffs
-
-RB_CCU_CNTL:
- - 0x3c400004 -> 0x3e400004
- - 0x10000000 -> 0x08000000
-
-RB_UNKNOWN_8E04: <-- see stencil-0000.rd.gz
- - 0x01000000 -> 0x00100000
-
-SP_UNKNOWN_A0F8:
-PC_UNKNOWN_9805:
- - 0x1 -> 0
- */
- fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
- fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x7c000) |
- A6XX_RB_CCU_CNTL_GMEM |
- A6XX_RB_CCU_CNTL_UNK2;
- fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x10000);
- fd6_ctx->magic.PC_UNKNOWN_9805 = 0x0;
- fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x0;
- break;
- case 630:
- fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x01000000;
- fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
- A6XX_RB_CCU_CNTL_GMEM |
- A6XX_RB_CCU_CNTL_UNK2;
- fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
- fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
- fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
- break;
- case 640:
- fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x00100000;
- fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0xf8000) |
- A6XX_RB_CCU_CNTL_GMEM;
- fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x20000);
- fd6_ctx->magic.PC_UNKNOWN_9805 = 0x1;
- fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x1;
- break;
- case 650:
- fd6_ctx->magic.RB_UNKNOWN_8E04_blit = 0x04100000;
- fd6_ctx->magic.RB_CCU_CNTL_gmem = A6XX_RB_CCU_CNTL_OFFSET(0x114000) |
- A6XX_RB_CCU_CNTL_GMEM;
- fd6_ctx->magic.RB_CCU_CNTL_bypass = A6XX_RB_CCU_CNTL_OFFSET(0x30000);
- fd6_ctx->magic.PC_UNKNOWN_9805 = 0x2;
- fd6_ctx->magic.SP_UNKNOWN_A0F8 = 0x2;
- break;
- default:
- unreachable("missing magic config");
- }
-
pctx = &fd6_ctx->base.base;
pctx->screen = pscreen;
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_context.h b/src/gallium/drivers/freedreno/a6xx/fd6_context.h
index 8305345421a..1ae97d47c91 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_context.h
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_context.h
@@ -106,17 +106,6 @@ struct fd6_context {
uint16_t tex_seqno;
struct hash_table *tex_cache;
- /* collection of magic register values which differ between
- * various different a6xx
- */
- struct {
- uint32_t RB_UNKNOWN_8E04_blit; /* value for CP_BLIT's */
- uint32_t RB_CCU_CNTL_bypass; /* for sysmem rendering */
- uint32_t RB_CCU_CNTL_gmem; /* for GMEM rendering */
- uint32_t PC_UNKNOWN_9805;
- uint32_t SP_UNKNOWN_A0F8;
- } magic;
-
struct {
/* previous binning/draw lrz state, which is a function of multiple
* gallium stateobjs, but doesn't necessarily change as frequently:
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
index c9630f21838..c68ae9445cc 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_draw.c
@@ -343,7 +343,7 @@ static void
fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
{
struct fd_ringbuffer *ring;
- struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
+ struct fd_screen *screen = batch->ctx->screen;
ring = fd_batch_get_prologue(batch);
@@ -354,8 +354,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_bypass);
+ OUT_REG(ring, A6XX_RB_CCU_CNTL(.offset = screen->info.a6xx.ccu_offset_bypass));
OUT_REG(ring, A6XX_HLSQ_INVALIDATE_CMD(
.vs_state = true,
@@ -443,7 +442,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_WFI5(ring);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
- OUT_RING(ring, fd6_ctx->magic.RB_UNKNOWN_8E04_blit);
+ OUT_RING(ring, screen->info.a6xx.magic.RB_UNKNOWN_8E04_blit);
OUT_PKT7(ring, CP_BLIT, 1);
OUT_RING(ring, CP_BLIT_0_OP(BLIT_OP_SCALE));
diff --git a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
index 068bf93fbaf..47fe1307ef1 100644
--- a/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+++ b/src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
@@ -558,7 +558,7 @@ emit_binning_pass(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
- struct fd6_context *fd6_ctx = fd6_context(batch->ctx);
+ struct fd_screen *screen = batch->ctx->screen;
debug_assert(!batch->tessellation);
@@ -582,10 +582,10 @@ emit_binning_pass(struct fd_batch *batch)
update_vsc_pipe(batch);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
- OUT_RING(ring, fd6_ctx->magic.PC_UNKNOWN_9805);
+ OUT_RING(ring, screen->info.a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
- OUT_RING(ring, fd6_ctx->magic.SP_UNKNOWN_A0F8);
+ OUT_RING(ring, screen->info.a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_EVENT_WRITE, 1);
OUT_RING(ring, UNK_2C);
@@ -633,8 +633,10 @@ emit_binning_pass(struct fd_batch *batch)
OUT_WFI5(ring);
- OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, fd6_ctx->magic.RB_CCU_CNTL_gmem);
+ OUT_REG(ring,
+ A6XX_RB_CCU_CNTL(.offset = screen->info.a6xx.ccu_offset_gmem,
+ .gmem = true,
+ .unk2 = screen->info.a6xx.ccu_cntl_gmem_unk2));
}
static void
@@ -668,10 +670,10 @@ static void prepare_tile_fini_ib(struct fd_batch *batch);
static void
fd6_emit_tile_init(struct fd_batch *batch)
{
- struct fd_context *ctx = batch->ctx;
struct fd_ringbuffer *ring = batch->gmem;
struct pipe_framebuffer_state *pfb = &batch->framebuffer;
const struct fd_gmem_stateobj *gmem = batch->gmem_state;
+ struct fd_screen *screen = batch->ctx->screen;
fd6_emit_restore(batch, ring);
@@ -696,8 +698,10 @@ fd6_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, 0x1);
fd_wfi(batch, ring);
- OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.RB_CCU_CNTL_gmem);
+ OUT_REG(ring,
+ A6XX_RB_CCU_CNTL(.offset = screen->info.a6xx.ccu_offset_gmem,
+ .gmem = true,
+ .unk2 = screen->info.a6xx.ccu_cntl_gmem_unk2));
emit_zs(ring, pfb->zsbuf, batch->gmem_state);
emit_mrt(ring, pfb, batch->gmem_state);
@@ -732,10 +736,10 @@ fd6_emit_tile_init(struct fd_batch *batch)
OUT_RING(ring, 0x0);
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9805, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.PC_UNKNOWN_9805);
+ OUT_RING(ring, screen->info.a6xx.magic.PC_UNKNOWN_9805);
OUT_PKT4(ring, REG_A6XX_SP_UNKNOWN_A0F8, 1);
- OUT_RING(ring, fd6_context(ctx)->magic.SP_UNKNOWN_A0F8);
+ OUT_RING(ring, screen->info.a6xx.magic.SP_UNKNOWN_A0F8);
OUT_PKT7(ring, CP_SKIP_IB2_ENABLE_GLOBAL, 1);
OUT_RING(ring, 0x1);
@@ -1367,6 +1371,7 @@ static void
fd6_emit_sysmem_prep(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->gmem;
+ struct fd_screen *screen = batch->ctx->screen;
fd6_emit_restore(batch, ring);
fd6_emit_lrz_flush(ring);
@@ -1413,8 +1418,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch)
fd6_cache_inv(batch, ring);
fd_wfi(batch, ring);
- OUT_PKT4(ring, REG_A6XX_RB_CCU_CNTL, 1);
- OUT_RING(ring, fd6_context(batch->ctx)->magic.RB_CCU_CNTL_bypass);
+ OUT_REG(ring, A6XX_RB_CCU_CNTL(.offset = screen->info.a6xx.ccu_offset_bypass));
/* enable stream-out, with sysmem there is only one pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.c b/src/gallium/drivers/freedreno/freedreno_gmem.c
index 3f528800ae7..04447ffef03 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.c
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.c
@@ -178,13 +178,13 @@ layout_gmem(struct gmem_key *key, uint32_t nbins_x, uint32_t nbins_y,
return false;
uint32_t bin_w, bin_h;
- bin_w = div_align(key->width, nbins_x, screen->tile_alignw);
- bin_h = div_align(key->height, nbins_y, screen->tile_alignh);
+ bin_w = div_align(key->width, nbins_x, screen->info.tile_align_w);
+ bin_h = div_align(key->height, nbins_y, screen->info.tile_align_h);
- if (bin_w > screen->tile_maxw)
+ if (bin_w > screen->info.tile_max_w)
return false;
- if (bin_h > screen->tile_maxh)
+ if (bin_h > screen->info.tile_max_h)
return false;
gmem->bin_w = bin_w;
@@ -221,8 +221,8 @@ calc_nbins(struct gmem_key *key, struct fd_gmem_stateobj *gmem)
{
struct fd_screen *screen = gmem->screen;
uint32_t nbins_x = 1, nbins_y = 1;
- uint32_t max_width = screen->tile_maxw;
- uint32_t max_height = screen->tile_maxh;
+ uint32_t max_width = screen->info.tile_max_w;
+ uint32_t max_height = screen->info.tile_max_h;
if (fd_mesa_debug & FD_DBG_MSGS) {
debug_printf("binning input: cbuf cpp:");
@@ -235,11 +235,11 @@ calc_nbins(struct gmem_key *key, struct fd_gmem_stateobj *gmem)
/* first, find a bin size that satisfies the maximum width/
* height restrictions:
*/
- while (div_align(key->width, nbins_x, screen->tile_alignw) > max_width) {
+ while (div_align(key->width, nbins_x, screen->info.tile_align_w) > max_width) {
nbins_x++;
}
- while (div_align(key->height, nbins_y, screen->tile_alignh) > max_height) {
+ while (div_align(key->height, nbins_y, screen->info.tile_align_h) > max_height) {
nbins_y++;
}
@@ -280,7 +280,7 @@ gmem_stateobj_init(struct fd_screen *screen, struct gmem_key *key)
gmem->key = key;
list_inithead(&gmem->node);
- const unsigned npipes = screen->num_vsc_pipes;
+ const unsigned npipes = screen->info.num_vsc_pipes;
uint32_t i, j, t, xoff, yoff;
uint32_t tpp_x, tpp_y;
int tile_n[npipes];
@@ -500,8 +500,8 @@ gmem_key_init(struct fd_batch *batch, bool assume_zs, bool no_scis_opt)
}
/* round down to multiple of alignment: */
- key->minx = scissor->minx & ~(screen->gmem_alignw - 1);
- key->miny = scissor->miny & ~(screen->gmem_alignh - 1);
+ key->minx = scissor->minx & ~(screen->info.gmem_align_w - 1);
+ key->miny = scissor->miny & ~(screen->info.gmem_align_h - 1);
key->width = scissor->maxx - key->minx;
key->height = scissor->maxy - key->miny;
}
@@ -786,58 +786,6 @@ max_bitfield_val(unsigned high, unsigned low, unsigned shift)
return BITFIELD_MASK(high - low) << shift;
}
-void
-fd_gmem_init_limits(struct pipe_screen *pscreen)
-{
- struct fd_screen *screen = fd_screen(pscreen);
-
- switch (screen->gpu_id) {
- case 600 ... 699:
- screen->gmem_alignw = 16;
- screen->gmem_alignh = 4;
- screen->tile_alignw = is_a650(screen) ? 96 : 32;
- screen->tile_alignh = 32;
- /* based on GRAS_BIN_CONTROL: */
- screen->tile_maxw = 1024; /* max_bitfield_val(5, 0, 5) */
- screen->tile_maxh = max_bitfield_val(14, 8, 4);
- screen->num_vsc_pipes = 32;
- break;
- case 500 ... 599:
- screen->gmem_alignw = screen->tile_alignw = 64;
- screen->gmem_alignh = screen->tile_alignh = 32;
- /* based on VSC_BIN_SIZE: */
- screen->tile_maxw = 1024; /* max_bitfield_val(7, 0, 5) */
- screen->tile_maxh = max_bitfield_val(16, 9, 5);
- screen->num_vsc_pipes = 16;
- break;
- case 400 ... 499:
- screen->gmem_alignw = screen->tile_alignw = 32;
- screen->gmem_alignh = screen->tile_alignh = 32;
- /* based on VSC_BIN_SIZE: */
- screen->tile_maxw = 1024; /* max_bitfield_val(4, 0, 5) */
- screen->tile_maxh = max_bitfield_val(9, 5, 5);
- screen->num_vsc_pipes = 8;
- break;
- case 300 ... 399:
- screen->gmem_alignw = screen->tile_alignw = 32;
- screen->gmem_alignh = screen->tile_alignh = 32;
- /* based on VSC_BIN_SIZE: */
- screen->tile_maxw = 992; /* max_bitfield_val(4, 0, 5) */
- screen->tile_maxh = max_bitfield_val(9, 5, 5);
- screen->num_vsc_pipes = 8;
- break;
- case 200 ... 299:
- screen->gmem_alignw = screen->tile_alignw = 32;
- screen->gmem_alignh = screen->tile_alignh = 32;
- screen->tile_maxw = 512;
- screen->tile_maxh = ~0; // TODO
- screen->num_vsc_pipes = 8;
- break;
- default:
- unreachable("unsupported GPU");
- }
-}
-
void
fd_gmem_screen_init(struct pipe_screen *pscreen)
{
diff --git a/src/gallium/drivers/freedreno/freedreno_gmem.h b/src/gallium/drivers/freedreno/freedreno_gmem.h
index 1ea4da895db..6a98e260893 100644
--- a/src/gallium/drivers/freedreno/freedreno_gmem.h
+++ b/src/gallium/drivers/freedreno/freedreno_gmem.h
@@ -93,7 +93,6 @@ bool fd_gmem_needs_restore(struct fd_batch *batch, const struct fd_tile *tile,
uint32_t buffers);
struct pipe_screen;
-void fd_gmem_init_limits(struct pipe_screen *pscreen);
void fd_gmem_screen_init(struct pipe_screen *pscreen);
void fd_gmem_screen_fini(struct pipe_screen *pscreen);
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c b/src/gallium/drivers/freedreno/freedreno_resource.c
index 2851f6664ca..12cc2ee0ac2 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -1021,7 +1021,7 @@ fd_resource_create_with_modifiers(struct pipe_screen *pscreen,
struct winsys_handle handle;
/* note: alignment is wrong for a6xx */
- scanout_templat.width0 = align(tmpl->width0, screen->gmem_alignw);
+ scanout_templat.width0 = align(tmpl->width0, screen->info.gmem_align_w);
scanout = renderonly_scanout_for_resource(&scanout_templat,
screen->ro, &handle);
@@ -1113,14 +1113,14 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
slice->offset = handle->offset;
slice->size0 = handle->stride * prsc->height0;
- /* use a pitchalign of gmem_alignw pixels, because GMEM resolve for
+ /* use a pitchalign of gmem_align_w pixels, because GMEM resolve for
* lower alignments is not implemented (but possible for a6xx at least)
*
* for UBWC-enabled resources, layout_resource_for_modifier will further
* validate the pitch and set the right pitchalign
*/
rsc->layout.pitchalign =
- fdl_cpp_shift(&rsc->layout) + util_logbase2(screen->gmem_alignw);
+ fdl_cpp_shift(&rsc->layout) + util_logbase2(screen->info.gmem_align_w);
/* apply the minimum pitchalign (note: actually 4 for a3xx but doesn't matter) */
if (is_a6xx(screen) || is_a5xx(screen))
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c
index e4c4e611aa8..c5be17bf710 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -992,7 +992,7 @@ fd_screen_create(struct fd_device *dev, struct renderonly *ro)
goto fail;
}
- fd_gmem_init_limits(pscreen);
+ freedreno_dev_info_init(&screen->info, screen->gpu_id);
if (fd_mesa_debug & FD_DBG_PERFC) {
screen->perfcntr_groups = fd_perfcntrs(screen->gpu_id,
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.h b/src/gallium/drivers/freedreno/freedreno_screen.h
index 99a754475d8..bc1d8212a77 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.h
+++ b/src/gallium/drivers/freedreno/freedreno_screen.h
@@ -30,6 +30,7 @@
#include "drm/freedreno_drmif.h"
#include "drm/freedreno_ringbuffer.h"
#include "perfcntrs/freedreno_perfcntr.h"
+#include "common/freedreno_dev_info.h"
#include "pipe/p_screen.h"
#include "util/debug.h"
@@ -71,15 +72,13 @@ struct fd_screen {
uint32_t max_freq;
uint32_t ram_size;
uint32_t max_rts; /* max # of render targets */
- uint32_t gmem_alignw, gmem_alignh; /* gmem load/store granularity */
- uint32_t tile_alignw, tile_alignh; /* alignment for tile sizes */
- uint32_t tile_maxw, tile_maxh; /* max tile size */
- uint32_t num_vsc_pipes;
uint32_t priority_mask;
bool has_timestamp;
bool has_robustness;
bool has_syncobj;
+ struct freedreno_dev_info info;
+
unsigned num_perfcntr_groups;
const struct fd_perfcntr_group *perfcntr_groups;
diff --git a/src/gallium/drivers/freedreno/gmemtool.c b/src/gallium/drivers/freedreno/gmemtool.c
index 1303fbf8e64..b33642d53d1 100644
--- a/src/gallium/drivers/freedreno/gmemtool.c
+++ b/src/gallium/drivers/freedreno/gmemtool.c
@@ -167,7 +167,7 @@ main(int argc, char **argv)
.gmemsize_bytes = gpu_info->gmemsize_bytes,
};
- fd_gmem_init_limits(&screen.base);
+ freedreno_dev_info_init(&screen.info, gpu_info->gpu_id);
/* And finally run thru all the GMEM keys: */
for (int i = 0; i < ARRAY_SIZE(keys); i++) {
@@ -178,8 +178,8 @@ main(int argc, char **argv)
assert((gmem->bin_w * gmem->nbins_x) >= key.width);
assert((gmem->bin_h * gmem->nbins_y) >= key.height);
- assert(gmem->bin_w < screen.tile_maxw);
- assert(gmem->bin_h < screen.tile_maxh);
+ assert(gmem->bin_w < screen.info.tile_max_w);
+ assert(gmem->bin_h < screen.info.tile_max_h);
ralloc_free(gmem);
}
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