Mesa (master): nir: add shader_info::bit_sizes_used
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Wed Nov 4 12:08:03 UTC 2020
Module: Mesa
Branch: master
Commit: 4e5c85526b1c66a004d14e7b8ffa13b2bb0e706d
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e5c85526b1c66a004d14e7b8ffa13b2bb0e706d
Author: Rhys Perry <pendingchaos02 at gmail.com>
Date: Thu Oct 29 10:52:25 2020 +0000
nir: add shader_info::bit_sizes_used
Signed-off-by: Rhys Perry <pendingchaos02 at gmail.com>
Reviewed-by: Daniel Schürmann <daniel at schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4791>
---
src/compiler/nir/nir_gather_info.c | 17 +++++++++++++----
src/compiler/shader_info.h | 7 +++----
src/mesa/drivers/dri/i965/brw_program.c | 2 +-
src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
4 files changed, 18 insertions(+), 10 deletions(-)
diff --git a/src/compiler/nir/nir_gather_info.c b/src/compiler/nir/nir_gather_info.c
index 29c8aac1d21..2271f8b6b7a 100644
--- a/src/compiler/nir/nir_gather_info.c
+++ b/src/compiler/nir/nir_gather_info.c
@@ -712,11 +712,18 @@ gather_alu_info(nir_alu_instr *instr, nir_shader *shader)
break;
}
- shader->info.uses_64bit |= instr->dest.dest.ssa.bit_size == 64;
- unsigned num_srcs = nir_op_infos[instr->op].num_inputs;
- for (unsigned i = 0; i < num_srcs; i++) {
- shader->info.uses_64bit |= nir_src_bit_size(instr->src[i].src) == 64;
+ const nir_op_info *info = &nir_op_infos[instr->op];
+
+ for (unsigned i = 0; i < info->num_inputs; i++) {
+ if (nir_alu_type_get_base_type(info->input_types[i]) == nir_type_float)
+ shader->info.bit_sizes_float |= nir_src_bit_size(instr->src[i].src);
+ else
+ shader->info.bit_sizes_int |= nir_src_bit_size(instr->src[i].src);
}
+ if (nir_alu_type_get_base_type(info->output_type) == nir_type_float)
+ shader->info.bit_sizes_float |= nir_dest_bit_size(instr->dest.dest);
+ else
+ shader->info.bit_sizes_int |= nir_dest_bit_size(instr->dest.dest);
}
static void
@@ -749,6 +756,8 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.num_images = 0;
shader->info.image_buffers = 0;
shader->info.msaa_images = 0;
+ shader->info.bit_sizes_float = 0;
+ shader->info.bit_sizes_int = 0;
nir_foreach_uniform_variable(var, shader) {
/* Bindless textures and images don't use non-bindless slots.
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index f7c39044928..59d95416877 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -187,10 +187,9 @@ typedef struct shader_info {
*/
bool uses_fddx_fddy:1;
- /**
- * True if this shader uses 64-bit ALU operations
- */
- bool uses_64bit:1;
+ /* Bitmask of bit-sizes used with ALU instructions. */
+ uint8_t bit_sizes_float;
+ uint8_t bit_sizes_int;
/* Whether the first UBO is the default uniform buffer, i.e. uniforms. */
bool first_ubo_is_default_ubo:1;
diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c
index b3db2cc61bb..df3400a2677 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -119,7 +119,7 @@ brw_create_nir(struct brw_context *brw,
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- if (!ctx->SoftFP64 && nir->info.uses_64bit &&
+ if (!ctx->SoftFP64 && ((nir->info.bit_sizes_int | nir->info.bit_sizes_float) & 64) &&
(options->lower_doubles_options & nir_lower_fp64_full_software)) {
ctx->SoftFP64 = glsl_float64_funcs_to_nir(ctx, options);
}
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 91eaf8e967d..8c835e54bfe 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -370,7 +370,7 @@ st_nir_preprocess(struct st_context *st, struct gl_program *prog,
}
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
- if (!st->ctx->SoftFP64 && nir->info.uses_64bit &&
+ if (!st->ctx->SoftFP64 && ((nir->info.bit_sizes_int | nir->info.bit_sizes_float) & 64) &&
(options->lower_doubles_options & nir_lower_fp64_full_software) != 0) {
st->ctx->SoftFP64 = glsl_float64_funcs_to_nir(st->ctx, options);
}
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