Mesa (master): spirv: Implement SpvCapabilitySubgroupBufferBlockIOINTEL

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Module: Mesa
Branch: master
Commit: eb03f29655cb6324ebf8016048fb9c21878eb1f5
URL:    http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb03f29655cb6324ebf8016048fb9c21878eb1f5

Author: Caio Marcelo de Oliveira Filho <caio.oliveira at intel.com>
Date:   Mon Oct  5 14:49:15 2020 -0700

spirv: Implement SpvCapabilitySubgroupBufferBlockIOINTEL

Reviewed-by: Jason Ekstrand <jason at jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7448>

---

 src/compiler/shader_info.h         |  1 +
 src/compiler/spirv/spirv_to_nir.c  |  6 ++++++
 src/compiler/spirv/vtn_variables.c | 31 +++++++++++++++++++++++++++++++
 3 files changed, 38 insertions(+)

diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 7f655bb6ca5..8d77d5c3b7a 100644
--- a/src/compiler/shader_info.h
+++ b/src/compiler/shader_info.h
@@ -95,6 +95,7 @@ struct spirv_supported_capabilities {
    bool amd_image_gather_bias_lod;
 
    bool intel_subgroup_shuffle;
+   bool intel_subgroup_buffer_block_io;
 };
 
 typedef struct shader_info {
diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c
index 6eb7b8f258d..0f89a78431a 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -4397,6 +4397,10 @@ vtn_handle_preamble_instruction(struct vtn_builder *b, SpvOp opcode,
          spv_check_supported(intel_subgroup_shuffle, cap);
          break;
 
+      case SpvCapabilitySubgroupBufferBlockIOINTEL:
+         spv_check_supported(intel_subgroup_buffer_block_io, cap);
+         break;
+
       default:
          vtn_fail("Unhandled capability: %s (%u)",
                   spirv_capability_to_string(cap), cap);
@@ -5040,6 +5044,8 @@ vtn_handle_body_instruction(struct vtn_builder *b, SpvOp opcode,
    case SpvOpConvertUToPtr:
    case SpvOpGenericCastToPtrExplicit:
    case SpvOpGenericPtrMemSemantics:
+   case SpvOpSubgroupBlockReadINTEL:
+   case SpvOpSubgroupBlockWriteINTEL:
       vtn_handle_variables(b, opcode, w, count);
       break;
 
diff --git a/src/compiler/spirv/vtn_variables.c b/src/compiler/spirv/vtn_variables.c
index 1cc5c2bf8cc..7307457df40 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -2424,6 +2424,37 @@ vtn_handle_variables(struct vtn_builder *b, SpvOp opcode,
       break;
    }
 
+   case SpvOpSubgroupBlockReadINTEL: {
+      struct vtn_type *res_type = vtn_get_type(b, w[1]);
+      nir_deref_instr *src = vtn_nir_deref(b, w[3]);
+
+      nir_intrinsic_instr *load =
+         nir_intrinsic_instr_create(b->nb.shader,
+                                    nir_intrinsic_load_deref_block_intel);
+      load->src[0] = nir_src_for_ssa(&src->dest.ssa);
+      nir_ssa_dest_init_for_type(&load->instr, &load->dest,
+                                 res_type->type, NULL);
+      load->num_components = load->dest.ssa.num_components;
+      nir_builder_instr_insert(&b->nb, &load->instr);
+
+      vtn_push_nir_ssa(b, w[2], &load->dest.ssa);
+      break;
+   }
+
+   case SpvOpSubgroupBlockWriteINTEL: {
+      nir_deref_instr *dest = vtn_nir_deref(b, w[1]);
+      nir_ssa_def *data = vtn_ssa_value(b, w[2])->def;
+
+      nir_intrinsic_instr *store =
+         nir_intrinsic_instr_create(b->nb.shader,
+                                    nir_intrinsic_store_deref_block_intel);
+      store->src[0] = nir_src_for_ssa(&dest->dest.ssa);
+      store->src[1] = nir_src_for_ssa(data);
+      store->num_components = data->num_components;
+      nir_builder_instr_insert(&b->nb, &store->instr);
+      break;
+   }
+
    default:
       vtn_fail_with_opcode("Unhandled opcode", opcode);
    }